Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1433

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WCLK
BCLK
ADx
0
MSB
22.6.4 DSP
Figure 22-7 shpws the DSP interface format. DSP is a single-phase format,
I2S:AIFFMTCFG.DUAL_PHASE = 0, where WCLK is high for one BCLK period, followed by each audio
channel back-to-back. Data is sampled on the falling edge of BCLK and updated on the rising edge of
BCLK; this is configured by setting I2S:AIFFMTCFG.SMPL_EDGE = 0.
There is an optional IDLE period at the end of the clock phase between the last data channel and the next
WCLK period; logical 0 is output during this period. The number of BCLK cycles in the phase must be
equal to or higher than the word length, as specified in the I2S:AIFFMTCFG.WORD_LEN register, times
the number of specified channels (determined by the most significant 1 in all the I2S:AIFWMASKn
registers combined).
When sample words are back-to-back, LSB of the previous sample are output in the DATA DELAY cycle.
Figure 22-7. DSP Interface Format (Showing First Two of Eight Possible Channels)
WCLK
BCLK
A
Dx
n-1 n-2
MSB
SWCU117C – February 2015 – Revised September 2015
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Figure 22-6. RJF Interface Format
n-1 n-2 n-3 2 1
Left channel
WCLK period = 1/F
2 1 0
n-3
LSB
Channel 0 (left)
WCLK period = 1/F
Copyright © 2015, Texas Instruments Incorporated
0 n-1 n-2
LSB MSB
S
n-1 n-2 n-3 2
MSB
Channel 1 (right)
S
Integrated Interchip Sound (I2S) Module
Serial Interface Formats
n-3 2 1 0
LSB
Right channel
1 0 n-1
LSB
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