Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1389

www.ti.com
20.7.1.6 IMSC Register (Offset = 14h) [reset = 0h]
IMSC is shown in Figure 20-18
Interrupt Mask Set and Clear
31 30
23 22
15 14
7 6
RESERVED
Bit Field
31-4 RESERVED
3 TXIM
2 RXIM
1 RTIM
0 RORIM
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
and described in
Figure 20-18. IMSC Register
29 28
21 20
13 12
5 4
R-0h
Table 20-8. IMSC Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 20-8.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
TXIM RXIM
R/W-0h R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Transmit FIFO interrupt mask:
A read returns the current mask for transmit FIFO interrupt. On a
write of 1, the mask for transmit FIFO interrupt is set which means
the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears
the mask which means MIS.TXMIS will not reflect the interrupt.
Receive FIFO interrupt mask:
A read returns the current mask for receive FIFO interrupt. On a
write of 1, the mask for receive FIFO interrupt is set which means
the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears
the mask which means MIS.RXMIS will not reflect the interrupt.
Receive timeout interrupt mask:
A read returns the current mask for receive timeout interrupt. On a
write of 1, the mask for receive timeout interrupt is set which means
the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears
the mask which means MIS.RTMIS will not reflect the interrupt.
Receive overrun interrupt mask:
A read returns the current mask for receive overrun interrupt. On a
write of 1, the mask for receive overrun interrupt is set which means
the interrupt state will be reflected in MIS.RORMIS. A write of 0
clears the mask which means MIS.RORMIS will not reflect the
interrupt.
SSI Registers
26 25
18 17
10 9
2 1
RTIM
R/W-0h
Synchronous Serial Interface (SSI)
24
16
8
0
RORIM
R/W-0h
1389