Texas Instruments SimpleLink CC2620 Technical Reference Manual page 850

Cryptography Registers
Table 10-29. AESCTL Register Field Descriptions (continued)
Bit Field
18 CCM
17-16 RESERVED
15 CBC_MAC
14-9 RESERVED
8-7 CTR_WIDTH
6 CTR
5 CBC
4-3 KEY_SIZE
2 DIR
1 INPUT_RDY
0 OUTPUT_RDY
850
Type Reset Description
R/W 0h AES-CCM mode enable
AES-CCM is a combined mode, using AES for both authentication
and encryption.
Note: Selecting AES-CCM mode requires writing of
AESDATALEN1.LEN_MSW and AESDATALEN0.LEN_LSW after all
other registers.
Note: The CTR mode bit in this register must also be set to 1 to
enable AES-CTR.
selecting other AES modes than CTR mode is invalid.
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h MAC mode enable
The DIR bit must be set to 1 for this mode.
Selecting this mode requires writing the AESDATALEN1.LEN_MSW
and AESDATALEN0.LEN_LSW registers after all other registers.
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h
Specifies the counter width for AES-CTR mode
0h = 32_BIT : 32 bits
1h = 64_BIT : 64 bits
2h = 96_BIT : 96 bits
3h = 128_BIT : 128 bits
R/W 0h AES-CTR mode enable
This bit must also be set for CCM, when encryption or decryption is
required.
R/W 0h
CBC mode enable
R 0h This field specifies the key size.
The key size is automatically configured when a new key is loaded
through the key store module.
00 = N/A - reserved
01 = 128 bits
10 = N/A - reserved
11 = N/A - reserved
For the Crypto peripheral this field is fixed to 128 bits.
R/W 0h Direction.
0 : Decrypt operation is performed.
1 : Encrypt operation is performed.
This bit must be written with a 1 when CBC-MAC is selected.
R/W 0h If read as 1, this status bit indicates that the 16-byte AES input buffer
is empty. The Host is permitted to write the next block of data.
Writing a 0 clears the bit to zero and indicates that the AES engine
can use the provided input data block.
Writing a 1 to this bit will be ignored.
Note: For DMA operations, this bit is automatically controlled by the
Crypto peripheral.
After reset, this bit is 0. After writing a context (note 1), this bit will
become 1.
For typical use, this bit does NOT need to be written, but is used for
status reading only. In this case, this status bit is automatically
maintained by the Crypto peripheral.
R/W 0h If read as 1, this status bit indicates that an AES output block is
available to be retrieved by the Host.
Writing a 0 clears the bit to zero and indicates that output data is
read by the Host. The AES engine can provide a next output data
block.
Writing a 1 to this bit will be ignored.
Note: For DMA operations, this bit is automatically controlled by the
Crypto peripheral.
For typical use, this bit does NOT need to be written, but is used for
status reading only. In this case, this status bit is automatically
maintained by the Crypto peripheral.
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
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