Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1393

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20.7.1.10 DMACR Register (Offset = 24h) [reset = 0h]
DMACR is shown in
DMA Control
31 30
23 22
15 14
7 6
Bit Field
31-2 RESERVED
1 TXDMAE
0 RXDMAE
SWCU117C – February 2015 – Revised September 2015
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Figure 20-22 and described in
Figure 20-22. DMACR Register
29 28
RESERVED
21 20
RESERVED
13 12
RESERVED
5 4
RESERVED
R-0h
Table 20-12. DMACR Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 20-12.
27 26
R-0h
19 18
R-0h
11 10
R-0h
3 2
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Transmit DMA enable. If this bit is set to 1, DMA for the transmit
FIFO is enabled.
Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO
is enabled.
Synchronous Serial Interface (SSI)
SSI Registers
25 24
17 16
9 8
1 0
TXDMAE RXDMAE
R/W-0h R/W-0h
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