Trng Software Reset - Texas Instruments SimpleLink CC2620 Technical Reference Manual

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The TRNG core consists of two parts:
• The first part contains the FROs, whose output signals are sampled at regular intervals. The FROs are
asynchronous to one another and asynchronous to the sampling clock to make their behavior truly
nondeterministic. Each FRO has an error detection circuit that checks for repeating patterns coming
out of the FRO. If a repeating pattern is detected, the FRO is suspect of having locked onto the
sampling clock, which drastically reduces the amount of entropy generated by that FRO (this is
signaled as a FRO error event).
• The second part is the entropy accumulation circuit that uses an XOR tree to combine the sampled
FRO clock outputs and an 81-bit LFSR to accumulate entropy (TRNG:LFSR0, TRNG:LFSR1, and
TRNG:LFSR2 registers give the 81 bits main entropy accumulation LFSR).
The true entropy source is based upon a predetermined number of free-running oscillators (FROs). The
accumulation of timing jitter, caused (for the largest part) by shot noise, creates uncertainty intervals for
the output transitions of each FRO. Sampling within the uncertainly interval generates a small amount of
entropy, which is accumulated in an LFSR. Entropy generation with multiple FROs in parallel allows the
entropy accumulation to be done far more rapidly than is possible with one FRO.

16.3 TRNG Software Reset

A software reset of the module can be done by writing 1 to the TRNG:SWRESET.RESET register. When a
software reset completes the TRNG:SWRESET.RESET register is automatically reset to 0. By polling the
TRNG:SWRESET.RESET register for 0 the software can ensure that the reset is completed, the software
reset must be completed before doing any TRNG operations.
There is also a reset possibility from the PRCM module by writing a 1 to the
PRCM:RESETSECDMA.TRNG register, which is automatically reset. This reset enables the asynchronous
reset input to the module and not the internal reset, thus from a module perspective this is the same as
doing HW reset. SW must ensure that no access is done towards the TRNG while in reset state.
The software reset only resets the TRNG core and ensures the interconnect interface is not terminated
abnormally. The PRCM reset acts as a power-on reset for the module and thus, instantly terminates any
transactions and ongoing accumulation; therefore, care must be taken when using the PRCM reset
source—can safely be combined with a module clock gating prior to reset activation.
16.4 Interrupt Requests
An interrupt request, TRNG_IRQ, is generated when data is ready for transmission (or an alarm was
triggered). Table 16-1
Event Flag
TRNG:IRQSTAT.STAT
TRNG:IRQFLAGSTAT.RDY
TRNG:IRQFLAGSTAT.
SHUTDOWN_OVF
SWCU117C – February 2015 – Revised September 2015
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lists the event flags, and their masks, that can cause module interrupts.
Table 16-1. Events
Event Mask
TRNG:IRQFLAGMASK.RDY
and
TRNG:IRQFLAGMASK.
SHUTDOWN_OVF
TRNG:IRQFLAGMASK.RDY
TRNG:IRQFLAGMASK.
SHUTDOWN_OFV
Copyright © 2015, Texas Instruments Incorporated
Description
Not used, but can be read for combined status of the two
available interrupts
When 1, data is available in the TRNG:OUT1 and the
TRNG:OUT0 registers. Use TRNG:IRQFLAGCLR.RDY to
clear it.
When 1, the number of FROs shut down after a second
error event (the number of 1 bits in the
TRNG:ALARMSTOP register) has exceeded the threshold
set by the TRNG:ALARMCNT.SHUTDOWN_THR register.
Use the TRNG:IRQFLAGCLR.SHUTDOWN_OVF register
to clear it.
Random Number Generator
TRNG Software Reset
1159