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Functional Description
20.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1
Figure 20-6
shows the transfer signal sequence for Motorola SPI format with SPO = 0 and SPH = 1, which
covers both single and continuous transfers.
Figure 20-6. Motorola SPI Frame Format With SPO = 0 and SPH = 1
SSIn_Clk
SSIn_Fss
SSIn_Rx
SSIn_Tx
Note: Q is undefined.
In this configuration, the following occurs during idle periods:
•
SSIn_CLK is forced low
•
SSIn_FSS is forced high
•
The transmit data line SSIn_TX is arbitrarily forced low
•
When the SSI is configured as a master, it enables the SSIn_CLK pad
•
When the SSI is configured as a slave, it disables the SSIn_CLK pad
If the SSI is enabled and valid data is in the TX FIFO, the SSIn_FSS master signal goes low at the start of
transmission. The master SSIn_TX output is enabled. After an additional one-half SSIn_CLK period, both
master and slave valid data are enabled onto their respective transmission lines. At the same time,
SSIn_CLK is enabled with a rising-edge transition. Data is then captured on the falling edges and
propagated on the rising edges of the SSIn_CLK signal.
For a single-word transfer, after all bits are transferred, the SSIn_FSS line is returned to its IDLE high
state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transfers, the SSIn_FSS pin is held low between successive data words and
terminates like a single-word transfer.
1376
Synchronous Serial Interface (SSI)
Q
Q
MSB
MSB
Copyright © 2015, Texas Instruments Incorporated
4 to 16 bits
SWCU117C – February 2015 – Revised September 2015
www.ti.com
LSB
Q
LSB
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