Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1355

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19.7.1.7 LCRH Register (Offset = 2Ch) [reset = 0h]
LCRH is shown in
Line Control
31 30
23 22
15 14
7 6
SPS
R/W-0h
Bit Field
31-8 RESERVED
7 SPS
6-5 WLEN
4 FEN
3 STP2
2 EPS
1 PEN
SWCU117C – February 2015 – Revised September 2015
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Figure 19-10 and described in
Figure 19-10. LCRH Register
29 28
21 20
13 12
5 4
WLEN FEN
R/W-0h R/W-0h
Table 19-10. LCRH Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 19-10.
27
RESERVED
R/W-0h
19
RESERVED
R/W-0h
11
RESERVED
R/W-0h
3
STP2 EPS
R/W-0h R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
UART Stick Parity Select:
0: Stick parity is disabled
1: The parity bit is transmitted and checked as invert of EPS field
(i.e. the parity bit is transmitted and checked as 1 when EPS = 0).
This bit has no effect when PEN disables parity checking and
generation.
UART Word Length:
These bits indicate the number of data bits transmitted or received in
a frame.
0h = 5 : Word Length 5 bits
1h = 6 : Word Length 6 bits
2h = 7 : Word Length 7 bits
3h = 8 : Word Length 8 bits
UART Enable FIFOs
0h = FIFOs are disabled (character mode) that is, the FIFOs become
1-byte-deep holding registers.
1h = Transmit and receive FIFO buffers are enabled (FIFO mode)
UART Two Stop Bits Select:
If this bit is set to 1, two stop bits are transmitted at the end of the
frame. The receive logic does not check for two stop bits being
received.
UART Even Parity Select
0h = Odd parity: The UART generates or checks for an odd number
of 1s in the data and parity bits.
1h = Even parity: The UART generates or checks for an even
number of 1s in the data and parity bits.
UART Parity Enable
This bit controls generation and checking of parity bit.
0h = Parity is disabled and no parity bit is added to the data frame
1h = Parity checking and generation is enabled.
Universal Asynchronous Receivers and Transmitters (UARTS)
UARTS Registers
26 25
18 17
10 9
2 1
PEN
R/W-0h
24
16
8
0
BRK
R/W-0h
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