Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1422

2
I C Registers
21.5.1.13 MTPR Register (Offset = 80Ch) [reset = 1h]
MTPR is shown in
I2C Master Timer Period
This register specifies the period of the SCL clock.
31 30
23 22
15 14
7 6
TPR_7
R/W-0h
Bit Field
31-8 RESERVED
7 TPR_7
6-0 TPR
1422
Inter-Integrated Circuit (I
Figure 21-26 and described in
Figure 21-26. MTPR Register
29 28
21 20
13 12
5 4
Table 21-15. MTPR Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 1h
2
C) Interface
Copyright © 2015, Texas Instruments Incorporated
Table 21-15.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
TPR
R/W-1h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Must be set to 0 to set TPR. If set to 1, a write to TPR will be
ignored.
SCL clock period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the timer period register value (range of 1 to 127)
SCL_LP is the SCL low period (fixed at 6).
SCL_HP is the SCL high period (fixed at 4).
CLK_PRD is the system clock period in ns.
SWCU117C – February 2015 – Revised September 2015
26 25
18 17
10 9
2 1
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