Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1362

UARTS Registers
19.7.1.11 RIS Register (Offset = 3Ch) [reset = X]
RIS is shown in Figure 19-14
Raw Interrupt Status
31 30
23 22
15 14
7 6
FERIS RTRIS
R-0h R-0h
Bit Field
31-11 RESERVED
10 OERIS
9 BERIS
8 PERIS
7 FERIS
6 RTRIS
1362
Universal Asynchronous Receivers and Transmitters (UARTS)
and described in Table
Figure 19-14. RIS Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
TXRIS RXRIS
R-0h R-0h
Table 19-14. RIS Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
19-14.
27 26
19 18
11 10
OERIS
R-0h
3 2
RESERVED
R-3h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Overrun error interrupt status:
This field returns the raw interrupt state of the UART overrun error
interrupt. Overrun error occurs if data is received and the receive
FIFO is full.
Break error interrupt status:
This field returns the raw interrupt state of the UART break error
interrupt. Break error is set when a break condition is detected,
indicating that the received data input (UARTRXD input pin) was
held LOW for longer than a full-word transmission time (defined as
start, data, parity and stop bits).
Parity error interrupt status:
This field returns the raw interrupt state of the UART parity error
interrupt. Parity error is set if the parity of the received data character
does not match the parity that the LCRH.EPS and LCRH.SPS select.
Framing error interrupt status:
This field returns the raw interrupt state of the UART framing error
interrupt. Framing error is set if the received character does not have
a valid stop bit (a valid stop bit is 1).
Receive timeout interrupt status:
This field returns the raw interrupt state of the UART receive timeout
interrupt. The receive timeout interrupt is asserted when the receive
FIFO is not empty, and no more data is received during a 32-bit
period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data, or when a 1 is written
to ICR.RTIC.
The raw interrupt for receive timeout cannot be set unless the mask
is set (IMSC.RTIM = 1). This is because the mask acts as an enable
for power saving. That is, the same status can be read from
MIS.RTMIS and RTRIS.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
BERIS PERIS
R-0h R-0h
1 0
CTSRMIS RESERVED
R-X R-1h
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