Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1447

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22.10.1.7 AIFWMASK2 Register (Offset = 18h) [reset = 3h]
AIFWMASK2 is shown in
Word Selection Bit Mask for Pin 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-8 RESERVED
7-0 MASK
SWCU117C – February 2015 – Revised September 2015
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Figure 22-15 and described in
Figure 22-15. AIFWMASK2 Register
RESERVED
R-0h
Table 22-8. AIFWMASK2 Register Field Descriptions
Type Reset
R 0h
R/W 3h
Copyright © 2015, Texas Instruments Incorporated
Table 22-8.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Bit-mask indicating valid channels in a frame on AD2
In single-phase mode, each bit represents one channel, starting with
LSB for the first word in the frame. A frame can contain up to 8
channels. Channels that are not included in the mask will not be
sampled and stored in memory, and clocked out as '0'.
In dual-phase mode, only the two LSBs are considered. For a stereo
configuration, set both bits. For a mono configuration, set bit 0 only.
In mono mode, only channel 0 will be sampled and stored to
memory, and channel 0 will be repeated when clocked out.
In mono mode, only channel 0 will be sampled and stored to
memory, and channel 0 will be repeated in the second phase when
clocked out.
If all bits are zero, no input words will be stored to memory, and the
output data lines will be constant '0'. This can be utilized when PWM
debug output is desired without any actively used output pins.
Integrated Interchip Sound (I2S) Module
I2S Registers
8 7 6 5 4 3 2 1
MASK
R/W-3h
0
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