Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1211

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17.4.8.2 ADC Reference
The ADC supports two different internal references, one constant and one relative to VDDS.
The ADC automatically scales down the input signal to be within the reference range. It is possible to
disable the scaling, but this requires great care by the user to ensure the maximum ratings in the data
sheet are followed. With scaling enabled, the internal fixed reference looks like 4.3 V compared to the
actual input level. With scaling disabled, the reference is 1.47 V.
NOTE: With scaling disabled it is possible to cause permanent damage to the ADC with voltage
levels lower than VDDS. See the data sheet for detailed limits.
To save power in synchronous mode, the ADC reference can also be powered off during idle periods (if
the sampling period is long enough to turn it on again during sampling) by setting the
ADI_4_AUX:ADCREF0.REF_ON_IDLE register.
The ADC reference source is selected in the ADI_4_AUX:ADCREF0.SRC register and enabled in the
ADI_4_AUX:ADCREF0.EN register.
17.4.8.3 Sample Mode and Sample Duration
Sampling mode is configured in the ADI_4_AUX:ADC0.SMPL_MODE register.
Synchronous sampling is done by starting a sampling when a trigger is received. The input is then
sampled for a period defined in the ADI_4_AUX:ADC0.SMPL_CYCLE_EXP register before a conversion is
performed.
Asynchronous mode is always sampling; it only stops sampling when the start trigger occurs to perform a
conversion.
17.4.8.4 Input Signal Scaling
Disabling input scaling is configured through the ADI_4_AUX:ADC1.SCALE_DIS register, and can be
used to increase the ADC step resolution if the input signal is always below VDDR.
Use this setting with caution, as any input voltage above VDDR might damage the ADC permanently.
17.4.8.5 ADC Enable
Enabling the ADC analog core is done by setting the ADI_4_AUX:ADC0.EN register bit, which enables the
internal bias module and comparator.
17.4.8.6 Digital Core
The SAR ADC has a digital core that is used to configure the ADC, perform measurements, and interface
the AUX registers for control and data.
After configuring the ADC registers in ADI_4_AUX, the ADC digital core can be enabled. Any changes to
the ADC core or reference configuration (except for the enable signals) requires the ADC digital core to be
reset again to take effect. This reset is done by clearing and then setting the reset signal in the
ADI_4_AUX:ADC0.RESET_N register.
17.4.8.7 ADC Core Clock
The ADC core uses a 24-MHz clock source derived from SCLK_HF, which must be enabled by setting the
AUX_WUC:ADCCLKCTL.REQ register. When the corresponding ACK bit in the same register is read as
high, the clock is enabled to the ADC.
For accurate low-jitter sampling in asynchronous mode, the software must ensure that SCLK_HF is
sourced from the 24-MHz XTAL before using the ADC.
SWCU117C – February 2015 – Revised September 2015
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