Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1363

www.ti.com
Bit Field
5 TXRIS
4 RXRIS
3-2 RESERVED
1 CTSRMIS
0 RESERVED
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Table 19-14. RIS Register Field Descriptions (continued)
Type Reset
R 0h
R 0h
R 3h
R X
R 1h
Copyright © 2015, Texas Instruments Incorporated
Description
Transmit interrupt status:
This field returns the raw interrupt state of the UART transmit
interrupt.
When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is
asserted if the number of bytes in transmit FIFO is equal to or lower
than the programmed trigger level (IFLS.TXSEL). The transmit
interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt
through ICR.TXIC.
When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth
of one location, the transmit interrupt is asserted if there is no data
present in the transmitters single location. It is cleared by performing
a single write to the transmit FIFO, or by clearing the interrupt
through ICR.TXIC.
Receive interrupt status:
This field returns the raw interrupt state of the UART receive
interrupt.
When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is
asserted if the receive FIFO reaches the programmed trigger
level (IFLS.RXSEL). The receive interrupt is cleared by reading data
from the receive FIFO until it becomes less than the trigger level, or
by clearing the interrupt through ICR.RXIC.
When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth
of one location, the receive interrupt is asserted if data is received
thereby filling the location. The receive interrupt is cleared by
performing a single read of the receive FIFO, or by clearing the
interrupt through ICR.RXIC.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Clear to Send (CTS) modem interrupt status:
This field returns the raw interrupt state of the UART clear to send
interrupt.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Universal Asynchronous Receivers and Transmitters (UARTS)
UARTS Registers
1363