Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1424

2
I C Registers
21.5.1.15 MRIS Register (Offset = 814h) [reset = 0h]
MRIS is shown in Figure 21-28
Master Raw Interrupt Status
This register show the unmasked interrupt status.
31 30 29 28
15 14 13 12
Bit Field
31-1 RESERVED
0 RIS
1424
Inter-Integrated Circuit (I
and described in
Figure 21-28. MRIS Register
27 26 25
11 10 9
RESERVED
R-0h
Table 21-17. MRIS Register Field Descriptions
Type Reset
R 0h
R 0h
2
C) Interface
Copyright © 2015, Texas Instruments Incorporated
Table 21-17.
24 23 22 21
RESERVED
R-0h
8 7 6 5
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Raw interrupt status
0: No interrupt
1: A master interrupt is pending.
This bit is cleared by writing 1 to the MICR.IC bit .
SWCU117C – February 2015 – Revised September 2015
www.ti.com
20 19 18 17
4 3 2 1
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16
0
RIS
R-0h