Texas Instruments SimpleLink CC2620 Technical Reference Manual page 848

Cryptography Registers
10.2.1.18 AESIV_0 to AESIV_3 Register (Offset = 540h to 54Ch) [reset = 0h]
AESIV_0 to AESIV_3 is shown in
AES Initialization Vector
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-0 IV
848
Figure 10-20
Figure 10-20. AESIV_0 to AESIV_3 Register
Table 10-28. AESIV_0 to AESIV_3 Register Field Descriptions
Type Reset
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
and described in Table 10-28.
IV
R/W-0h
Description
The interpretation of this field depends on the crypto operation
mode.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
9 8 7 6 5 4 3 2
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