Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1309

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17.7.7.14 RTCSUBSECINCCTL Register (Offset = 44h) [reset = 0h]
RTCSUBSECINCCTL is shown in
Real Time Counter Sub Second Increment Control
31 30
23 22
15 14
7 6
Bit Field
31-2 RESERVED
1 UPD_ACK
0 UPD_REQ
SWCU117C – February 2015 – Revised September 2015
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Figure 17-75
Figure 17-75. RTCSUBSECINCCTL Register
29 28
21 20
13 12
5 4
RESERVED
R-0h
Table 17-100. RTCSUBSECINCCTL Register Field Descriptions
Type Reset
R 0h
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
and described in Table
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Acknowledgment of the UPD_REQ.
Signal that a new real time counter sub second increment value is
available
0: New sub-second increment is not available
1: New sub-second increment is available
This bit must not be modified unless UPD_ACK matches the current
value.
AUX – Sensor Controller with Digital and Analog Peripherals
AUX – Sensor Controller Registers
17-100.
26 25
18 17
10 9
2 1
UPD_ACK UPD_REQ
R-0h
24
16
8
0
R/W-0h
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