Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1199

www.ti.com
For instructions using direct memory addressing, a 10-bit address is embedded in the instruction word,
supporting direct access to 1K memory instructions in the range 0 to 1023. Using the prefix instruction, the
direct memory address can be extended to 16-bit, allowing direct access to 64K memory instructions.
16-bit addressing is also possible using one of the indirect or the indexed addressing modes.
The b<cc> disp instructions perform conditional branching depending on the condition code flags as listed
in Table 17-9.
Syntax <cc>
gtu
geu / iob0
eq / z
novf
pos
ges
gts
leu
ltu / iob1
neq / nz
ovf
neg
lts
les
When the condition tested is true, the next instruction is fetched from instruction memory at a location
equal to the sum of address of the instruction following the branch instruction, and an 8-bit signed
displacement in the range –128 to +127 embedded in the instruction word itself. When the condition
tested is false, instruction fetching continues sequentially. In addition to the above mentioned conditional
branches, an unconditional relative branch bra rel also exists.
The branch-event instructions bev0 and bev1 perform conditional branching, depending on event inputs
provided directly to the sensor controller from its event input. These are the same events as for the wev0
and wev1 instructions, and are described in
This branching allows efficient control processing based on external events. The instruction word embeds
a 3-bit event ID in the instruction word, directly supporting 8 external events, and more can be selected
using the prefix instruction.
Each event can be tested for being deasserted (0) or asserted (1). When the selected event input has the
expected value, the address of the next instruction to execute is determined using an 8-bit signed
displacement in the instruction word, as for the b<cc> disp instructions. When the selected event input
does not have the expected value, instruction fetching continues sequentially.
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Table 17-9. Conditional Branching
Description
Greater than, unsigned
Greater or equal, unsigned / Tested
register bit = 0
Equal / Zero
Not overflow
Positive
Greater or equal, signed
Greater than, signed
Less or Equal, unsigned
Less than, unsigned / Tested I/O bit = 1
Not Equal / Not Zero
Overflow
Negative
Less than, signed
Less or equal, signed
Section 17.4.2.1.2, Sensor Controller Events.
AUX – Sensor Controller with Digital and Analog Peripherals
Copyright © 2015, Texas Instruments Incorporated
Condition
!C & !Z
!C
Z
!V
!N
(N & V) | (!N & !V)
( (N & V) | (!N & !V) ) & !Z
C | Z
C
!Z
V
N
(N & !V) | (!N & V)
(N & !V) | (!N & V) | Z
Modules
1199