Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1081

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Prescale (8-bit Value)
00000000
00000001
00000010
–
11111101
11111110
11111111
(1)
Tc is the clock period.
13.3.2.2 Input Edge-count Mode
NOTE: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be low for
at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is ¼ of the system frequency.
In edge-count mode, the timer is configured as a 24-bit down counter, including the optional prescaler with
the upper count value stored in the GPTM Timer n Prescale Register (GPT:TnPR) and the lower bits in
the GPT:TnR register. In this mode, the timer is capable of capturing three types of events: rising edge,
falling edge, or both. To place the timer in edge-count mode, the GPT:TnMR register TnCMR bit must be
cleared. The type of edge that the timer counts is determined by the GPT:CTL register TnEVENT fields.
During initialization in down-count mode, the GPT:TnMATCHR and the GPT:TnPMR registers are
configured so that the difference between the value in the GPT:TnILR and the GPT:TnPR registers and
the GPT:TnMATCHR and the GPT:TnPMR registers equals the number of edge events that must be
counted. In up-count mode, the timer counts from 0x0 to the value in the GPT:TnMATCHR and the
GPT:TnPMR registers.
enabled.
Table 13-3. Counter Values When the Timer is Enabled in Input Edge-Count Mode
Register
GPT:TnR
GPT:TnV
GPT:TnPV
When software writes the GPTM Control Register (GPT:CTL) TnEN bit, the timer is enabled for event
capture. Each input event on the CCP pin decrements or increments the counter by 1 until the event count
matches the GPT:TnMATCHR and the GPT:TnPMR registers. When the counts match, the GPTM asserts
the GPTM Raw Interrupt Status Register (GPT:RIS) CnMRIS bit, and holds the bit until it is cleared by
writing the GPTM Interrupt Clear Register (GPT:ICR). If the capture mode match interrupt is enabled in
the GPTM Interrupt Mask Register (GPT:IMR), the GPTM also sets the GPTM Masked Interrupt Status
Register (GPT:MIS) CnMMIS bit. In this mode, the GPT:TnR register holds the count of the input events
while the GPT:TnV and the GPT:TnPV registers hold the free-running timer value and the free-running
prescaler value.
In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled by
configuring and enabling the appropriate μDMA channel.
After the match value is reached in down-count mode, the counter is then reloaded using the value in the
GPT:TnILR and the GPT:TnPR registers, and stopped because the GPTM automatically clears the
GPT:CTL TnEN register bit. Once the event count has been reached, all further events are ignored until
the TnEN bit is re-enabled by software. In up-count mode, the timer is reloaded with 0x0 and continues
counting.
SWCU117C – February 2015 – Revised September 2015
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Table 13-2. 16-bit Timer With Prescaler Configurations
(1)
# of Timer Clocks (Tc)
1
2
3
–
254
255
256
Table 13-3 lists the values that are loaded into the timer registers when the timer is
Count Down Mode
GPT:TnILR
GPT:TnILR
GPT:TnPR
Copyright © 2015, Texas Instruments Incorporated
Maximum Time
2.7
5.4
8.1
–
685.8
688.5
691.2
Count Up Mode
0x0
0x0
0x0
Functional Description
Unit
ms
ms
ms
–
ms
ms
ms
1081
Timers