Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1150

Watchdog Timer Registers
15.4.1.3 CTL Register (Offset = 8h) [reset = 0h]
CTL is shown in Figure 15-4
Control
31 30
23 22
15 14
7 6
Bit Field
31-3 RESERVED
2 INTTYPE
1 RESEN
0 INTEN
1150
Watchdog Timer
and described in Table
Figure 15-4. CTL Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 15-4. CTL Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
15-4.
27 26
19 18
11 10
3 2
INTTYPE
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
WDT Interrupt Type
0: WDT interrupt is a standard interrupt.
1: WDT interrupt is a non-maskable interrupt.
0h = Maskable interrupt
1h = Non-maskable interrupt
WDT Reset Enable. Defines the function of the WDT reset source
(see PRCM:WARMRESET.WDT_STAT if enabled)
0: Disabled.
1: Enable the Watchdog reset output.
0h = Reset output Disabled
1h = Reset output Enabled
WDT Interrupt Enable
0: Interrupt event disabled.
1: Interrupt event enabled. Once set, this bit can only be cleared by
a hardware reset.
0h = Interrupt Disabled
1h = Interrupt Enabled
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
1 0
RESEN INTEN
R/W-0h R/W-0h
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