Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1082

Functional Description
Figure 13-2 shows how Input edge-count mode works. In this case, the timer start value is set to
GPT:TnILR = 0x000A, and the match value is set to GPT:TnMATCHR = 0x0006 so that four edge events
are counted. The counter is configured to detect both edges of the input signal.
NOTE: The last two edges are not counted, because the timer automatically clears the TnEN bit
after the current count matches the value in the GPT:TnMATCHR register.
Figure 13-2. Input Edge-count Mode Example, Counting Down
Count
0x000A
0x0009
0x0008
0x0007
0x0006
Input Signal
13.3.2.3 Input Edge-time Mode
NOTE: For rising-edge detection, the input signal must be high for at least two system-clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be low for
at least two system-clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is ¼ of the system frequency.
In edge-time mode, the timer is configured as a 24-bit down counter, including the optional prescaler with
the upper timer value stored in the GPT:TnPR register and the lower bits in the GPT:TnILR register. In this
mode, the timer is initialized to the value loaded in the GPT:TnILR and the GPT:TnPR registers when
counting down and 0x0 when counting up. The timer is capable of capturing three types of events: rising
edge, falling edge, or both. The timer is placed into edge-time mode by setting the GPT:TnMR TnCM
register bit, and the type of event that the timer captures is determined by the GPT:CTL TnEVENT register
fields. Table 13-4 lists the values that are loaded into the timer registers when the timer is enabled.
Table 13-4. Counter Values When the Timer is Enabled in Input Event-Count Mode
Register
GPT:TnR
GPT:TnV
GPT:TnPV
When software writes to the GPT:CTL TnEN register bit, the timer is enabled for event capture. When the
selected input event is detected, the current timer counter value is captured in the GPT:TnR register and
is available to be read by the microcontroller. The GPTM then asserts the GPTM Raw Interrupt Status
Register (GPT:RIS) CnERIS bit, and holds the bit until it is cleared by writing the GPTM Interrupt Clear
Register (GPT:ICR). If the capture mode event interrupt is enabled in the GPTM Interrupt Mask Register
1082
Timers
Timer stops,
flags
asserted
Count Down Mode
GPT:TnILR
GPT:TnILR
GPT:TnPR
Copyright © 2015, Texas Instruments Incorporated
Timer reload
on next cycle
Ignored Ignored
Count Up Mode
0x0
0x0
0x0
SWCU117C – February 2015 – Revised September 2015
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