Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1065

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12.5.1.9 SETREQMASK Register (Offset = 20h) [reset = 0h]
SETREQMASK is shown in
Channel Set Request Mask
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-0 CHNLS
SWCU117C – February 2015 – Revised September 2015
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Figure 12-15 and described in
Figure 12-15. SETREQMASK Register
CHNLS
R/W-0h
Table 12-16. SETREQMASK Register Field Descriptions
Type Reset
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 12-16.
9
Description
Returns the burst and single request mask status, or disables the
corresponding channel from generating uDMA requests.
Read as:
Bit [Ch] = 0: External requests are enabled for channel Ch.
Bit [Ch] = 1: External requests are disabled for channel Ch.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable
uDMA requests.
Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA
single request channel [C] input from generating uDMA requests.
Writing to a bit where a uDMA channel is not implemented has no
effect
Micro Direct Memory Access (µDMA)
µDMA Registers
8 7 6 5 4 3 2 1 0
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