Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1195

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17.4.1.4.1 wev1, wev0, and sleep Instructions
The wev1, wev0, and sleep instructions take a parameter that is an event number (event 0 to 7). When
the instruction is executed, the clock stops until the selected event line reaches 0 for a wev0 instruction or
1 for a wev1 instruction. The events are described in
Section 17.4.2.1.2, Sensor Controller Events.
The sleep instruction stops the clock and also triggers the AUX power domain to go into a low-power
mode if AUX is set up to do so. See
The sensor controller continues execution from one of its four input wake-up vectors in the
AUX_EVCTL:VECCFG0 and the AUX_EVCTL:VECCFG1 registers, which are prioritized from 0 (highest)
to 3 (lowest).
17.4.1.5 Instruction Set
The sensor controller instruction set is compact, powerful, and highly regular. The sensor controller is
based on the traditional RISC concept of having all operands in the registers, or in an immediate field
embedded directly in the instruction opcode.
Data memory can only be accessed using load and store operations, while I/O ports can be accessed
using input and output instructions as well as special bit-manipulation instructions.
For dyadic operations, the destination register appears to the left in the mnemonic except for memory and
I/O operations, where the memory and port address is always the right operand.
The following sections describes all instructions. Each table shows the instruction, the mnemonic, an
informal and a formal description of the operation performed, and how the flags zero (Z), negative (N),
carry (C), and overflow (V) are updated. The operation description is described as right-associative.
17.4.1.5.1 Memory Access
The sensor controller load and store (ld and st) instructions allow reading and writing data from or to the
AUX_RAM.
Load and store instructions transfer data between an integer register and a location in the data memory,
the address of which is determined by the current addressing mode.
Table 17-3 lists the load and store instructions.
Syntax Description
ld Rd,addr Load direct
ld Rd,(Rs) Load indirect
Load indirect, post-
ld Rd,(Rs)++
increment
ld Rd,(Rs+R0) Load indexed
st Rd,addr Store direct
st Rd,(Rs) Store indirect
Store indirect, post-
st Rd,(Rs)++
increment
st Rd,(Rs+r0) Store indexed
(1)
Flags: Zero (Z), Negative (N), Carry (C), and Overflow (V)
For instructions using direct-memory addressing, a 10-bit address is embedded in the instruction word,
supporting direct access to 1K memory words in the range 0 to 1023. Using the prefix instruction, the
direct-memory address can be extended to 16-bit, allowing direct access to 64K memory words. 16-bit
addressing of memory is also possible using indirect or indexed addressing.
SWCU117C – February 2015 – Revised September 2015
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Section
Section 17.5, Power Management, for more details.
Table 17-3. Load and Store Instructions
Operation
Rd = mem[addr]
Rd = mem[Rs]
Rd = mem[Rs], Rs++
Rd = mem[Rs+R0]
mem[addr] = Rd
mem[Rs] = Rd
mem[Rs] = Rd, Rs++
mem[Rs+r0] = Rd
AUX – Sensor Controller with Digital and Analog Peripherals
Copyright © 2015, Texas Instruments Incorporated
17.4.2.1, Event Control, and
(1)
Z N
– –
– –
– –
– –
– –
– –
– –
– –
Modules
C V
– –
– –
– –
– –
– –
– –
– –
– –
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