Texas Instruments SimpleLink CC2620 Technical Reference Manual page 849

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10.2.1.19 AESCTL Register (Offset = 550h) [reset = 80000000h]
AESCTL is shown in
AES Input/Output Buffer Control
31 30
CONTEXT_RD SAVED_CONT
Y EXT_RDY
R-1h R/W-0h
23 22
CCM_M
R/W-0h
15 14
CBC_MAC
R/W-0h
7 6
CTR_WIDTH CTR
R/W-0h R/W-0h
Bit Field
31 CONTEXT_RDY
30 SAVED_CONTEXT_RDY
29 SAVE_CONTEXT
28-25 RESERVED
24-22 CCM_M
21-19 CCM_L
SWCU117C – February 2015 – Revised September 2015
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Figure 10-21 and described in
Figure 10-21. AESCTL Register
29 28
SAVE_CONTE
XT
R/W-0h
21 20
CCM_L
R/W-0h
13 12
RESERVED
5 4
CBC KEY_SIZE
R/W-0h
Table 10-29. AESCTL Register Field Descriptions
Type Reset
R 1h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 10-29.
27 26
RESERVED
R/W-0h
19 18
CCM
R/W-0h
11 10
R/W-0h
3 2
DIR
R-0h R/W-0h
Description
If 1, this status bit indicates that the context data registers can be
overwritten and the Host is permitted to write the next context.
Writing a context means writing either a mode, the crypto length or
AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length
registers
If read as 1, this status bit indicates that an AES authentication TAG
and/or IV block (or blocks) is/are available for the Host to retrieve.
This bit is only asserted if SAVE_CONTEXT is set to 1. The bit is
mutually exclusive with CONTEXT_RDY.
Writing 1 clears the bit to zero, indicating the Crypto peripheral can
start its next operation. This bit is also cleared when the fourth word
of the output TAG and/or IV is read.
Note: All other mode bit writes will be ignored when this mode bit is
written with 1.
Note: This bit is controlled automatically by the Crypto peripheral for
TAG read DMA operations.
For typical use, this bit does NOT need to be written, but is used for
status reading only. In this case, this status bit is automatically
maintained by the Crypto peripheral.
IV must be read before the AES engine can start a new operation.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Defines M that indicates the length of the authentication field for
CCM operations.
The authentication field length equals two times the value of CCM_M
plus one.
Note: The Crypto peripheral always returns a 128-bit authentication
field, of which the M least significant bytes are valid. All values are
supported.
Defines L that indicates the width of the length field for CCM
operations.
The length field in bytes equals the value of CMM_L plus one. All
values are supported.
Cryptography Registers
25 24
CCM_M
R/W-0h
17 16
RESERVED
R/W-0h
9 8
CTR_WIDTH
R/W-0h
1 0
INPUT_RDY OUTPUT_RDY
R/W-0h R/W-0h
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