Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1125

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13.5.1.29 ANDCCP Register (Offset = FB4h) [reset = 0h]
ANDCCP is shown in
Combined CCP Output
This register is used to logically AND CCP output pairs for each timer
31 30
23 22
15 14
7 6
Bit Field
31-1 RESERVED
0 CCP_AND_EN
SWCU117C – February 2015 – Revised September 2015
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Figure 13-37 and described in
Figure 13-37. ANDCCP Register
29 28
RESERVED
21 20
RESERVED
13 12
RESERVED
5 4
RESERVED
R-0h
Table 13-36. ANDCCP Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 13-36.
27 26
R-0h
19 18
R-0h
11 10
R-0h
3 2
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Enables AND operation of the CCP outputs for timers A and B.
0 : PWM outputs of Timer A and Timer B are the internal generated
PWM signals of the respective timers.
1 : PWM output of Timer A is ANDed version of Timer A and Timer B
PWM signals and Timer B PWM ouput is Timer B PWM signal only.
General-purpose Timer Registers
25 24
17 16
9 8
1 0
CCP_AND_EN
R/W-0h
Timers
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