Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1449

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22.10.1.9 AIFINPTRNEXT Register (Offset = 20h) [reset = 0h]
AIFINPTRNEXT is shown in
DMA Input Buffer Next Pointer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-0 PTR
SWCU117C – February 2015 – Revised September 2015
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Figure 22-17 and described in
Figure 22-17. AIFINPTRNEXT Register
PTR
R/W-0h
Table 22-10. AIFINPTRNEXT Register Field Descriptions
Type Reset
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 22-10.
9
Description
Pointer to the first byte in the next DMA input buffer.
The read value equals the last written value until the currently used
DMA input buffer is completed, and then becomes null when the last
written value is transferred to the DMA controller to start on the next
buffer. This event is signalized by aif_dma_in_irq.
At startup, the value must be written once before and once after
configuring the DMA buffer size in AIFDMACFG.
The next pointer must be written to this register while the DMA
function uses the previously written pointer. If not written in time,
IRQFLAGS.PTR_ERR will be raised and all input pins will be
disabled.
Note the following limitations:
- Address space wrapping is not supported. That means address(last
sample) must be higher than address(first sample.
- A DMA block cannot be aligned with the end of the address space,
that means a block cannot contain the address 0xFFFF.
Integrated Interchip Sound (I2S) Module
I2S Registers
8 7 6 5 4 3 2 1 0
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