Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1133

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14.4.1.2 EVFLAGS Register (Offset = 4h) [reset = 0h]
EVFLAGS is shown in
Event Flags—RTC Status
This register contains event flags from the 3 RTC channels. Each flag is cleared when writing a 1 to the
corresponding bit field.
31 30 29 28
15 14 13 12
RESERVED
R-0h
Bit Field
31-17 RESERVED
16 CH2
15-9 RESERVED
8 CH1
7-1 RESERVED
0 CH0
SWCU117C – February 2015 – Revised September 2015
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Figure 14-3 and described in
Figure 14-3. EVFLAGS Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
CH1
R/W1
C-0h
Table 14-3. EVFLAGS Register Field Descriptions
Type Reset
R 0h
R/W1C 0h
R 0h
R/W1C 0h
R 0h
R/W1C 0h
Copyright © 2015, Texas Instruments Incorporated
Table 14-3.
23 22 21 20
7 6 5 4
RESERVED
R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC
value matches or passes the CH2CMP value.
An event will be scheduled to occur as soon as possible when
writing to CH2CMP provided that the channel is enabled and the
new value matches any time between next RTC value and 1 second
in the past.
Writing 1 clears this flag. Note that a new event can not occur on this
channel in first 2 SCLK_LF cycles after a clearance.
AUX_SCE can read the flag through
AUX_WUC:WUEVFLAGS.AON_RTC and clear it using
AUX_WUC:WUEVCLR.AON_RTC.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the
following:
CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes
the CH1CMP value.
CHCTL.CH1_CAPT_EN = 1 and capture occurs.
An event will be scheduled to occur as soon as possible when
writing to CH1CMP provided that the channel is enabled, in compare
mode and the new value matches any time between next RTC value
and 1 second in the past.
Writing 1 clears this flag. Note that a new event can not occur on this
channel in first 2 SCLK_LF cycles after a clearance.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC
value matches or passes the CH0CMP value.
An event will be scheduled to occur as soon as possible when
writing to CH0CMP provided that the channels is enabled and the
new value matches any time between next RTC value and 1 second
in the past.
Writing 1 clears this flag. Note that a new event can not occur on this
channel in first 2 SCLK_LF cycles after a clearance.
Real-Time Clock Registers
19 18 17 16
CH2
R/W1
C-0h
3 2 1 0
CH0
R/W1
C-0h
1133
Real-Time Clock