Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1626

Zigbee rf4ce wireless mcu simplelink cc13 series; simplelink cc26 series

Radio Registers

23.8.3.1 PWMCLKEN Register (Offset = 0h) [reset = 1h]

PWMCLKEN is shown in

RF Core Power Management and Clock Enable

Figure 23-30

and described in

Figure 23-30. PWMCLKEN Register

Table 23-175. PWMCLKEN Register Field Descriptions

Software must not rely on the value of a reserved. Writing any other

value than the reset value may result in undefined behavior.

Enable clock to the RF Core Tracer (RFCTRC) module.

Enable clock to the Frequency Synthesizer Calibration Accelerator

(FSCA) module.

Enable clock to the Packet Handling Accelerator (PHA) module.

Enable clock to the Radio Timer (RAT) module.

Enable clock to the RF Engine RAM module.

Enable clock to the RF Engine (RFE) module.

Enable clock to the Modem RAM module.

Enable clock to the Modem (MDM) module.

Enable clock to the Command and Packet Engine (CPE) RAM

module. As part of RF Core initialization, set this bit together with

CPE bit to enable CPE to boot.

Enable processor clock (hclk) to the Command and Packet Engine

(CPE). As part of RF Core initialization, set this bit together with

CPERAM bit to enable CPE to boot.

Enable essential clocks for the RF Core interface. This includes the

interconnect, the radio doorbell DBELL command interface, the

power management (PWR) clock control module, and bus clock

(sclk) for the CPE. To remove possibility of locking yourself out from

the RF Core, this bit can not be cleared. If you need to disable all

clocks to the RF Core, see the PRCM:RFCCLKG.CLK_EN register.

SWCU117C – February 2015 – Revised September 2015

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