Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1208

Modules
17.4.4.1 Configuration
The TDC must be in idle mode to be configured; any register writes are ignored when not in idle mode.
The TDC starts up in idle and returns to idle when a measurement is done or a measurement is aborted.
17.4.4.2 Clocks
Before accessing the TDC module, the clock to the TDC interface must be enabled by writing to the
AUX_WUC:MODCLKEN0.TDC register.
The high-speed clock used to count must also be configured in the
DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL register.
Clock Source
RCOSC_HF
RCOSC_HF_D24M
XOSC_HF_D24M
See Section 17.4.6, Oscillator Configuration Interface (DDI), for information on writing to the oscillator
interface.
If the TDC is used to measure the frequency of another on-chip frequency oscillator, the correct low-
frequency source must be configured in the DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL register.
Table 17-18 lists the available reference clock sources.
Clock Source
RCOSC_HF_DLF
XOSC_HF_DLF
RCOSC_LF
XOSC_LF
Before using the TDC, the above-configured clock sources must be enabled by writing to the
AUX_WUC:TDCCLKCTL.REQ and the AUX_WUC:REFCLKCTL.REQ register. The corresponding ACK
bit is set when the clock source has started and is ready to use.
NOTE: If there are any high-speed clocks enabled for the TDC, the system is not able to go to
standby mode because the oscillator is still requesting resources from the supply system.
17.4.4.2.1 Start and Stop Source
A start and stop source must be configured for the TDC before doing a measurement by configuring the
AUX_TDC:TRIGSRC register. It is also possible to configure the polarity of the start and stop sources,
which lets the TDC start or stop counting on the programmed edge.
If more than one period of a signal is to be measured, the number of stop events to ignore before stopping
the measurement must be configured in the AUX_TDC:TRIGCNTLOAD register, and the stop counter
must be enabled in the AUX_TDC:TRIGCNTCFG register.
17.4.4.2.2 Saturation
The TDC can be configured in the AUX_TDC:SATCFG register to saturate and stop the measurement if
the counter values are larger than a configurable saturation limit. This process can be useful when an
unknown signal is input as start or stop source to limit the maximum time the TDC is counting. If the TDC
saturates, both the SAT and DONE status bits are set in the AUX_TDC:STAT register.
1208
AUX – Sensor Controller with Digital and Analog Peripherals
Table 17-17. Available Clock Sources
Table 17-18. Available Reference Clock Sources
Copyright © 2015, Texas Instruments Incorporated
Table 17-17 lists the available clock sources.
Description
48-MHz RCOSC
24 MHz derived from RCOSC_HF
24 MHz derived from XOSC_HF
Description
Clock derived from 48-MHz RCOSC (31.25 kHz)
Clock derived from 2-4MHz XOSC (31.25 kHz)
Clock from RCOSC_LF (32 kHz)
Clock from XOSC_LF (32.768 kHz)
SWCU117C – February 2015 – Revised September 2015
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