Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1360

UARTS Registers
19.7.1.10 IMSC Register (Offset = 38h) [reset = 0h]
IMSC is shown in Figure 19-13
Interrupt Mask Set/Clear
31 30
23 22
15 14
7 6
FEIM RTIM
R/W-0h R/W-0h
Bit Field
31-11 RESERVED
10 OEIM
9 BEIM
8 PEIM
7 FEIM
6 RTIM
5 TXIM
1360
Universal Asynchronous Receivers and Transmitters (UARTS)
and described in
Figure 19-13. IMSC Register
29 28
RESERVED
R/W-0h
21 20
RESERVED
R/W-0h
13 12
RESERVED
R/W-0h
5 4
TXIM RXIM
R/W-0h R/W-0h
Table 19-13. IMSC Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 19-13.
27 26
19 18
11 10
OEIM
R/W-0h
3 2
RESERVED
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Overrun error interrupt mask. A read returns the current mask for the
UART overrun error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.OEMIS. A write of 0 clears the mask, which means
MIS.OEMIS will not reflect the interrupt.
Break error interrupt mask. A read returns the current mask for the
UART break error interrupt. On a write of 1, the mask of the overrun
error interrupt is set which means the interrupt state will be reflected
in MIS.BEMIS. A write of 0 clears the mask, which means
MIS.BEMIS will not reflect the interrupt.
Parity error interrupt mask. A read returns the current mask for the
UART parity error interrupt. On a write of 1, the mask of the overrun
error interrupt is set which means the interrupt state will be reflected
in MIS.PEMIS. A write of 0 clears the mask, which means
MIS.PEMIS will not reflect the interrupt.
Framing error interrupt mask. A read returns the current mask for the
UART framing error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.FEMIS. A write of 0 clears the mask, which means
MIS.FEMIS will not reflect the interrupt.
Receive timeout interrupt mask. A read returns the current mask for
the UART receive timeout interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.RTMIS. A write of 0 clears the mask which means
this bit field will not reflect the interrupt.
The raw interrupt for receive timeout RIS.RTRIS cannot be set
unless the mask is set (RTIM = 1). This is because the mask acts as
an enable for power saving. That is, the same status can be read
from MIS.RTMIS and RIS.RTRIS.
Transmit interrupt mask. A read returns the current mask for the
UART transmit interrupt. On a write of 1, the mask of the overrun
error interrupt is set which means the interrupt state will be reflected
in MIS.TXMIS. A write of 0 clears the mask, which means
MIS.TXMIS will not reflect the interrupt.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
BEIM PEIM
R/W-0h R/W-0h
1 0
CTSMIM RESERVED
R/W-0h R/W-0h
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