Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1410

2
I C Registers
21.5.1.2 SSTAT Register (Offset = 4h) [reset = 0h]
SSTAT is shown in
Slave Status
Internal Note: This register shares address with SCTL, meaning that this register functions as a control
register when written, and a status register when read.
31 30
23 22
15 14
7 6
Bit Field
31-3 RESERVED
2 FBR
1 TREQ
0 RREQ
1410
Inter-Integrated Circuit (I
Figure 21-15 and described in
Figure 21-15. SSTAT Register
29 28
21 20
13 12
5 4
RESERVED
R-0h
Table 21-4. SSTAT Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
2
C) Interface
Copyright © 2015, Texas Instruments Incorporated
Table 21-4.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
FBR
R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
First byte received
0: The first byte has not been received.
1: The first byte following the slave's own address has been
received.
This bit is only valid when the RREQ bit is set and is automatically
cleared when data has been read from the SDR register.
Note: This bit is not used for slave transmit operations.
Transmit request
0: No outstanding transmit request.
1: The I2C controller has been addressed as a slave transmitter and
is using clock stretching to delay the master until data has been
written to the SDR register.
Receive request
0: No outstanding receive data
1: The I2C controller has outstanding receive data from the I2C
master and is using clock stretching to delay the master until data
has been read from the SDR register.
SWCU117C – February 2015 – Revised September 2015
26 25
18 17
10 9
2 1
TREQ
R-0h
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24
16
8
0
RREQ
R-0h