Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1415

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21.5.1.7 SMIS Register (Offset = 14h) [reset = 0h]
SMIS is shown in Figure 21-20
Slave Masked Interrupt Status
This register show which interrupt is active (based on result from SRIS and SIMR).
31 30
23 22
15 14
7 6
Bit Field
31-3 RESERVED
2 STOPMIS
1 STARTMIS
0 DATAMIS
SWCU117C – February 2015 – Revised September 2015
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and described in
Figure 21-20. SMIS Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 21-9. SMIS Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 21-9.
27 26
19 18
11 10
3 2
STOPMIS
R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Stop condition masked interrupt status
0: An interrupt has not occurred or is masked/disabled.
1: An unmasked Stop condition interrupt is pending.
This bit is cleared by writing a 1 to the SICR.STOPIC.
Start condition masked interrupt status
0: An interrupt has not occurred or is masked/disabled.
1: An unmasked Start condition interrupt is pending.
This bit is cleared by writing a 1 to the SICR.STARTIC.
Data masked interrupt status
0: An interrupt has not occurred or is masked/disabled.
1: An unmasked data received or data requested interrupt is
pending.
This bit is cleared by writing a 1 to the SICR.DATAIC.
Inter-Integrated Circuit (I
2
I C Registers
25 24
17 16
9 8
1 0
STARTMIS DATAMIS
R-0h R-0h
1415
2
C) Interface