Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1419

www.ti.com
21.5.1.11 MCTRL Register (Offset = 804h) [reset = 0h]
MCTRL is shown in
Master Control
This register accesses status bits when read and control bits when written. When read, the status register
indicates the state of the I2C bus controller as stated in MSTAT. When written, the control register
configures the I2C controller operation.
To generate a single transmit cycle, the I2C Master Slave Address (MSA) register is written with the
desired address, the MSA.RS bit is cleared, and this register is written with
* ACK=X (0 or 1),
* STOP=1,
* START=1,
* RUN=1
to perform the operation and stop.
When the operation is completed (or aborted due an error), an interrupt becomes active and the data may
be read from the MDR register.
31 30
23 22
15 14
7 6
RESERVED
Bit Field
31-4 RESERVED
3 ACK
2 STOP
1 START
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Figure 21-24 and described in
Figure 21-24. MCTRL Register
29 28
21 20
13 12
5 4
W-0h
Table 21-13. MCTRL Register Field Descriptions
Type Reset
W 0h
W 0h
W 0h
W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 21-13.
27
RESERVED
W-0h
19
RESERVED
W-0h
11
RESERVED
W-0h
3
ACK STOP
W-0h W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Data acknowledge enable
0: The received data byte is not acknowledged automatically by the
master.
1: The received data byte is acknowledged automatically by the
master.
This bit-field must be cleared when the I2C bus controller requires
no further data to be transmitted from the slave transmitter.
0h = Disable acknowledge
1h = Enable acknowledge
This bit-field determines if the cycle stops at the end of the data
cycle or continues on to a repeated START condition.
0: The controller does not generate the Stop condition.
1: The controller generates the Stop condition.
0h = Disable STOP
1h = Enable STOP
This bit-field generates the Start or Repeated Start condition.
0: The controller does not generate the Start condition.
1: The controller generates the Start condition.
0h = Disable START
1h = Enable START
I
26 25
18 17
10 9
2 1
START
W-0h
2
Inter-Integrated Circuit (I C) Interface
2
C Registers
24
16
8
0
RUN
W-0h
1419