Texas Instruments SimpleLink CC2620 Technical Reference Manual page 1095

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13.5.1.3 TBMR Register (Offset = 8h) [reset = 0h]
TBMR is shown in
Timer B Mode
31 30
23 22
15 14
TCACT
R/W-0h
7 6
TBSNAPS TBWOT
R/W-0h R/W-0h
Bit Field
31-16 RESERVED
15-13 TCACT
12 TBCINTD
11 TBPLO
10 TBMRSU
9 TBPWMIE
SWCU117C – February 2015 – Revised September 2015
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Figure 13-11 and described in
Figure 13-11. TBMR Register
29 28
21 20
13 12
TBCINTD
R/W-0h
5 4
TBMIE TBCDIR
R/W-0h R/W-0h
Table 13-10. TBMR Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 13-10.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
TBPLO TBMRSU
R/W-0h R/W-0h
3
TBAMS TBCM
R/W-0h R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Timer Compare Action Select
0h = DIS_CMP : Disable compare operations
1h = Toggle State on Time-Out
2h = Clear CCP output pin on Time-Out
3h = Set CCP output pin on Time-Out
4h = Set CCP output pin immediately and toggle on Time-Out
5h = Clear CCP output pin immediately and toggle on Time-Out
6h = Set CCP output pin immediately and clear on Time-Out
7h = Clear CCP output pin immediately and set on Time-Out
One-Shot/Periodic Interrupt Mode
0h = Normal Time-Out Interrupt
1h = Mask Time-Out Interrupt
Legacy PWM operation
0h = Legacy operation
1h = CCP output pin is set to 1 on time-out
Timer B Match Register Update mode
This bit defines when the TBMATCHR and TBPR registers are
updated
If the timer is disabled (CTL.TBEN is clear) when this bit is set,
TBMATCHR and TBPR are updated when the timer is enabled.
If the timer is stalled (CTL.TBSTALL is set) when this bit is set,
TBMATCHR and TBPR are updated according to the configuration
of this bit.
0h = Update TBMATCHR and TBPR, if used on the next cycle.
1h = Update the TBMATCHR and the TBPR, if used on the next
time-out.
GPT Timer B PWM Interrupt Enable. This bit enables interrupts in
PWM mode on rising, falling, or both edges of the CCP output
0h = Interrupt is disabled.
1h = Interrupt is enabled. This bit is only valid in PWM mode.
General-purpose Timer Registers
26 25
18 17
10 9
TBPWMIE
R/W-0h
2 1
TBMR
R/W-0h
Timers
24
16
8
TBILD
R/W-0h
0
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