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Appendix H Power-On and Power-Off Procedures
• Power-on
Supply the internal power after supplying power to the I/O, PLL, RTC, and CPG. *
Supply power to V
At power-on, the RESET signal is low. Normally, supply power to the I/O, RTC, and CPG
before (or at the same time as) entering the signal lines (RESET, SCK2, MD0 to MD10,
and external clock). If the signal lines are entered first, the LSI may be damaged.
Input high level to SCK2 (MRESET) in compliance with the voltage level of the I/O, PLL,
RTC, CPG power supply voltage.
• Power-off
When turning off the power, there are no restrictions for the timing of RESET and SCK2.
Turn off the I/O, PLL, RTC, CPG power supply voltage after (or at the same time as) *
turning off the internal power supply voltage.
Note however that the internal power supply voltage may exceed the I/O, PLL, RTC, CPG
power supply voltage by a maximum of 0.3 V only when the system is being turned off.
The power supply level must be lowered in compliance with the I/O, PLL, RTC, CPG
power supply voltage.
Note: *1 10 ms or less for the HD6417750R.
• The ratings and procedures for power-on and power-off are given below.
V
= V
SSQ
SS-PLL1
The LSI may be damaged if
−0.3 V < V
in
−0.3 V < V
DD
are not satisfied when V
2.0 V
1.2 V
GND
0 ≤ t
Note: * HD6417750R only
Rev. 6.0, 07/02, page 978 of 986
, V
, V
DDQ
DD-PLL1/2
DD-RTC
= V
= V
= V
SS-PLL2
SS-RTC
< V
+ 0.3 V
DDQ
< V
+ 0.3 V
DDQ
= V
= V
DDQ
DD-RTC
Power-on
t
on
< 10 ms*
on
Figure H.1 Power-On and Power-Off Procedures
, and V
simultaneously.
DD-CPG
= 0 V
SS-CPG
.
DD-CPG
V
DDQ
V
DD
Power-off
t
off
0 ≤ t
< 10 ms*
off
1
1
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