Hitachi SH7750 Hardware Manual page 1035

Sh7750 series superh risc engine
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Serial Communication Interface with FIFO
............................................................ 657
Asynchronous Mode ........................... 685
Break................................................... 698
Smart Card Interface............................... 703
bit rate ................................................. 715
System Registers................................. 42, 50
Floating-point status/control register .... 51
FPSCR .................................................. 51
MACH .................................................. 50
MACL................................................... 50
Multiply-and-accumulate register high. 50
Multiply-and-accumulate register low.. 50
PC ......................................................... 50
PR ......................................................... 50
Procedure register ................................. 50
Program counter.................................... 50
T
Timer Unit............................................... 291
Auto-Reload Count Operation ............ 305
Input Capture Function ....................... 307
TCNT Count Timing........................... 306
U
User Break Controller ............................. 773
Instruction Access Cycle Break .......... 788
Operand Access Cycle Break.............. 789
User Break Debug Support Function .. 793
User Break Operation Sequence ......... 787
W
Watchdog Timer ............................. 247, 259
Interval Timer Mode ........................... 265
Watchdog Timer Mode ....................... 264
Rev. 6.0, 07/02, page 985 of 986

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