Figure 7-13 Essi Clock Generator Functional Block Diagram - Motorola DSP56305 User Manual

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
CRB(TE1)
SCn0
Sync:
TD1, or
Flag0
CRB(SCD0)
Async:
RX clk
SCKn
Sync:
TX/RX clk
Async:
CRB(SCKD)
TX clk
/2
F
CORE

Figure 7-13 ESSI Clock Generator Functional Block Diagram

7.4.1.4 Frame Rate Divider Control DC[4:0] CRA Bits 16-12
The DC[4:0] bits determine the division factor used by a frame rate divider to generate
an RX or TX frame sync signal from its respective word clock, when that frame sync is
configured as internally sourced (an output). This is depicted in Figure 7-14. For a
divide-by-N, the value (N-1) must be loaded into DC[4:0].
Note that although the RX and TX word widths will always be the same (according to
CRA(WL[2:0])), the RX and TX word clock rates will differ if their respective bit clock
rates are not the same. This can occur if one or both of these clocks are externally
sourced. If this is the case, then the RX and TX frame clock rates will differ accordingly.
DC[4:0] are cleared by hardware and software reset.
7-16
TD1 or Flag0 Out Flag0 In
CRB(OF0) SSISR(IF0)
(Sync Mode) (Sync Mode)
CRB(SYN) = 1
SYN = 0 SCD0 = 1
Internal Bit Clock
CRA(PSR)
CRA(PM7:0)
/1 or /8 /1 to /256
1 0 0
(Opposite
from SSI)
DSP56305 User's Manual
/8, /12, /16, /24, /32
SCD0 = 0
SYN = 0
RX Shift Register
RCLOCK
SYN = 1
TCLOCK
/8, /12, /16, /24, /32
0
TX Shift Registers
Note: 1.
2.
3.
255
CRA(WL2:0)
0 1 2 3 4,5
CRA(WL2:0)
1 2 3 4,5
F is the DSP56300 core
core
internal clock frequency.
ESSI internal clock range:
min = F /4096, max = F
core core
'n' in signal name is
ESSI (0 or 1)
AA0679
MOTOROLA
RX
Word
Clock
TX
Word
Clock
/4