Motorola DSP56305 User Manual page 71

Table 2-8 External Bus Control Signals (Continued)
Signal
Type
Name
BR Output
BG Input
MOTOROLA
State During
Reset, Wait,
or Stop
Driven High Bus Request—BR is asserted when the DSP or the
(Deasserted) DMA requests bus mastership. BR is deasserted when
the DSP or the DMA no longer needs the bus. BR may
be asserted or deasserted independent of whether the
DSP56305 is a bus master or a bus slave. Bus "parking"
allows BR to be deasserted even though the DSP56305
is the bus master (see the description of bus "parking"
in the BB signal description). The Bus Request Hole
(BRH) bit in the BCR allows BR to be asserted under
software control even though the DSP does not need
the bus. BR is typically sent to an external bus
arbitrator that controls the priority, parking, and
tenure of each master on the same external bus. BR is
only affected by DSP requests for the external bus,
never for the internal bus. During hardware reset, BR
is deasserted and the arbitration is reset to the bus
slave state. BR is never tri-stated.
Ignored Bus Grant—BG is asserted by an external bus
Input arbitration circuit when the DSP56305 becomes the
next bus master. BG must be asserted/deasserted
synchronous to CLKOUT for proper operation. When
BG is asserted, the DSP56305 must wait until BB is
deasserted before taking bus mastership. When BG is
deasserted, bus mastership is typically given up at the
end of the current bus cycle. This may occur in the
middle of an instruction that requires more than one
external bus cycle for execution.
DSP56305 User's Manual
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
Signal Description
2-13