Viterbi Butterfly Implementation; Figure 13-16 Viterbi Butterfly Structure - Motorola DSP56305 User Manual

24-bit digital signal processor
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13.7

VITERBI BUTTERFLY IMPLEMENTATION

Bits enter the Trellis state Least Significant Bit first (i.e. from right to left). As an example,
assume a16-state trellis (constraint length = 5). Let w, x, y, z each denote a binary digit so
that 'wxyz' represents a state in the trellis. The Viterbi butterfly is then defined as a
transition from the current states '0xyz' and '1xyz' to the next states 'xyz0' and 'xyz1' as
shown in Figure 13-16.
Decode
BM
0xyz
BM
1xyz
In Decode mode, a Branch Metric (BM) value is evaluated for each butterfly. In general,
BM is a weighted value of the received data symbols with reference to the expected
convolutional encoded bits of that particular state.
In Equalization mode, the BM for each transition within a Viterbi butterfly is a function
of the Matched Filter output (MF) and the L-Metric Viterbi Parameters (VP). The VP
values come from the channel sounding. After extracting the channel impulse response
coefficients via a cross correlation process (also referred to as the S parameters), the VP
value for a particular state 'wxyz' is usually calculated as follows:
(
VP w x y z
For full flexibility, calculating the VP values is done by software within the DSP core.
Notice that VP values are symmetric,
storage of only half of the L-metric table in the VP RAM. For a 64-state trellis (constraint
length equals 7), the VP values for each state are calculated in an analogous way making
use of S parameters S
MOTOROLA
xyz0
xyz1

Figure 13-16 Viterbi Butterfly Structure

w
, , ,
)
(
)
=
1 –
S
4
VP w x y z
to S
.
1
7
DSP56305 User's Manual
Viterbi Butterfly Implementation
0xyz
1xyz
x
y
(
)
(
)
+
1 –
S
+
1 –
3
(
, , ,
)
(
=
VP w x y z
VITERBI CO-PROCESSOR
Equalization
(MF–VP
)
0xyz
xyz0
–(MF–VP
)
1xyz
xyz1
z
(
)
S
+
1 –
S
2
1
, , ,
)
, thus requiring the
AA1325
13-33

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