Motorola DSP56012 Manuals

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Motorola DSP56012 User Manual

Motorola DSP56012 User Manual (270 pages)

24-Bit Digital Signal Processor  
Brand: Motorola | Category: Stereo System | Size: 2.31 MB
Table of contents
Table Of Contents3................................................................................................................................................................
List Of Figures13................................................................................................................................................................
Introduction23................................................................................................................................................................
Manual Organization24................................................................................................................................................................
Manual Conventions25................................................................................................................................................................
Dsp56012 Features26................................................................................................................................................................
Dsp56012 Architectural Overview28................................................................................................................................................................
Peripheral Modules30................................................................................................................................................................
Dsp Core Processor30................................................................................................................................................................
Data Arithmetic And Logic Unit (data Alu)31................................................................................................................................................................
Address Generation Unit (agu)31................................................................................................................................................................
Program Control Unit32................................................................................................................................................................
Data Buses32................................................................................................................................................................
Address Buses32................................................................................................................................................................
Phase Lock Loop (pll)32................................................................................................................................................................
On-chip Emulation (once) Port33................................................................................................................................................................
Memories33................................................................................................................................................................
Program Memory33................................................................................................................................................................
X Data Memory35................................................................................................................................................................
Y Data Memory35................................................................................................................................................................
On-chip Memory Configuration Bits35................................................................................................................................................................
Memory Configuration Bits36................................................................................................................................................................
External Memory36................................................................................................................................................................
Bootstrap Rom36................................................................................................................................................................
Reserved Memory Spaces36................................................................................................................................................................
Input/output36................................................................................................................................................................
Parallel Host Interface (hi)38................................................................................................................................................................
Serial Host Interface (shi)38................................................................................................................................................................
Serial Audio Interface (sai)39................................................................................................................................................................
General Purpose I/o39................................................................................................................................................................
Digital Audio Transmitter (dax)39................................................................................................................................................................
Signal Groupings43................................................................................................................................................................
Power45................................................................................................................................................................
Ground46................................................................................................................................................................
Interrupt And Mode Control48................................................................................................................................................................
Host Interface (hi)50................................................................................................................................................................
Sai Receive Section56................................................................................................................................................................
Sai Transmit Section57................................................................................................................................................................
General Purpose Input/output (gpio)58................................................................................................................................................................
Digital Audio Interface (dax)58................................................................................................................................................................
Once Port59................................................................................................................................................................
Dsp56012 Data And Program Memory63................................................................................................................................................................
Dsp56012 Data And Program Memory Maps64................................................................................................................................................................
X And Y Data Rom64................................................................................................................................................................
Dynamic Switch Of Memory Configurations68................................................................................................................................................................
Internal I/o Memory Map70................................................................................................................................................................
Operating Mode Register (omr)72................................................................................................................................................................
Dsp Operating Mode (mc, Mb, Ma)—bits 4, 1, And 072................................................................................................................................................................
Stop Delay (sd)—bit 672................................................................................................................................................................
Program Ram Enable A And Program Ram Enable B (pea And Peb)—bits 2 And72................................................................................................................................................................
Operating Modes73................................................................................................................................................................
Interrupt Priority Register75................................................................................................................................................................
Phase Lock Loop (pll) Configuration79................................................................................................................................................................
Operation On Hardware Reset80................................................................................................................................................................
Port B Configuration83................................................................................................................................................................
Port B Control (pbc) Register86................................................................................................................................................................
Port B Data Direction Register (pbddr)87................................................................................................................................................................
Port B Data (pbd) Register87................................................................................................................................................................
Programming The Gpio88................................................................................................................................................................
Hi Features90................................................................................................................................................................
Hi Block Diagram91................................................................................................................................................................
Hi—dsp Viewpoint92................................................................................................................................................................
Programming Model—dsp Viewpoint93................................................................................................................................................................
Hi Control Register (hcr)94................................................................................................................................................................
Hcr Hi Receive Interrupt Enable (hrie)—bit 095................................................................................................................................................................
Icr Hi Mode Control (hm1 And Hm0)—bits 5 And106................................................................................................................................................................
Icr Initialize Bit (init)—bit 7107................................................................................................................................................................
Hi Initialization107................................................................................................................................................................
Command Vector Register (cvr)109................................................................................................................................................................
Cvr Hi Vector (hv)—bits 0–5109................................................................................................................................................................
Cvr Reserved—bit 6110................................................................................................................................................................
Cvr Host Command (hc)—bit 7110................................................................................................................................................................
Interrupt Status Register (isr)110................................................................................................................................................................
Isr Receive Data Register Full (rxdf)—bit 0110................................................................................................................................................................
Isr Transmit Data Register Empty (txde)—bit 1111................................................................................................................................................................
Isr Transmitter Ready (trdy)—bit 2111................................................................................................................................................................
Unsynchronized Reading Of Receive Byte145................................................................................................................................................................
Overwriting Transmit Byte Registers146................................................................................................................................................................
Synchronization Of Status Bits From Dsp To Host146................................................................................................................................................................
Overwriting The Host Vector146................................................................................................................................................................
Cancelling A Pending Host Command Interrupt146................................................................................................................................................................
Coordinating Data Transfers147................................................................................................................................................................
Unused Pins147................................................................................................................................................................
Serial Host Interface Internal Architecture152................................................................................................................................................................
Shi Clock Generator153................................................................................................................................................................
Serial Host Interface Programming Model153................................................................................................................................................................
Shi Input/output Shift Register (iosr)—host Side156................................................................................................................................................................
Shi Host Transmit Data Register (htx)—dsp Side156................................................................................................................................................................
Shi Host Receive Data Fifo (hrx)—dsp Side157................................................................................................................................................................
Shi Slave Address Register (hsar)—dsp Side157................................................................................................................................................................
Hsar Reserved Bits—bits 17–0,19157................................................................................................................................................................
Hckr Divider Modulus Select (hdm[5:0])—bits 8–3160................................................................................................................................................................
Hckr Reserved Bits—bits 23–14, 11–9160................................................................................................................................................................
Hckr Filter Mode (hfm[1:0]) — Bits 13–12160................................................................................................................................................................
Shi Control/status Register (hcsr)—dsp Side161................................................................................................................................................................
Hcsr Host Enable (hen)—bit 0161................................................................................................................................................................
Shi Individual Reset161................................................................................................................................................................
Hcsr Fifo-enable Control (hfifo)—bit 5162................................................................................................................................................................
Hcsr Master Mode (hmst)—bit 6162................................................................................................................................................................
Hcsr Host-request Enable (hrqe[1:0])—bits 8–7163................................................................................................................................................................
Hcsr Idle (hidle)—bit 9163................................................................................................................................................................
Hcsr Receive Interrupt Enable (hrie[1:0])—bits164................................................................................................................................................................
Hcsr Bus-error Interrupt Enable (hbie)—bit 10164................................................................................................................................................................
Hcsr Transmit-interrupt Enable (htie)—bit 11164................................................................................................................................................................
Host Receive Overrun Error (hroe)—bit 20166................................................................................................................................................................
Host Bus Error (hber)—bit 21166................................................................................................................................................................
Hcsr Host Busy (hbusy)—bit 22167................................................................................................................................................................
Characteristics Of The Spi Bus167................................................................................................................................................................
Overview168................................................................................................................................................................
Shi Programming Considerations171................................................................................................................................................................
Spi Slave Mode171................................................................................................................................................................
Spi Master Mode172................................................................................................................................................................
Shi Operation During Stop178................................................................................................................................................................
Serial Audio Interface Internal Architecture182................................................................................................................................................................
Baud-rate Generator182................................................................................................................................................................
Receive Section Overview183................................................................................................................................................................
Sai Transmit Section Overview184................................................................................................................................................................
Serial Audio Interface Programming Model186................................................................................................................................................................
Baud Rate Control Register (brc)187................................................................................................................................................................
Prescale Modulus Select (pm[7:0])—bits 7–0188................................................................................................................................................................
Prescaler Range (psr)—bit 8188................................................................................................................................................................
Brc Reserved Bits—bits 15–9188................................................................................................................................................................
Receiver Control/status Register (rcs)188................................................................................................................................................................
Rcs Receiver 0 Enable (r0en)—bit 0188................................................................................................................................................................
Rcs Receiver 1 Enable (r1en)—bit 1189................................................................................................................................................................
Rcs Reserved Bit—bits 13 And 2189................................................................................................................................................................
Rcs Receiver Master (rmst)—bit 3189................................................................................................................................................................
Rcs Receiver Data Shift Direction (rdir)—bit 6190................................................................................................................................................................
Rcs Receiver Left Right Selection (rlrs)—bit 7190................................................................................................................................................................
Rcs Receiver Clock Polarity (rckp)—bit 8191................................................................................................................................................................
Rcs Receiver Relative Timing (rrel)—bit 9191................................................................................................................................................................
Rcs Receiver Data Word Truncation (rdwt)—bit192................................................................................................................................................................
Rcs Receiver Interrupt Enable (rxie)—bit 11193................................................................................................................................................................
Rcs Receiver Interrupt Location (rxil)—bit 12193................................................................................................................................................................
Rcs Receiver Left Data Full (rldf)—bit 14194................................................................................................................................................................
Rcs Receiver Right Data Full (rrdf)—bit 15194................................................................................................................................................................
Sai Receive Data Registers (rx0 And Rx1)195................................................................................................................................................................
Transmitter Control/status Register (tcs)195................................................................................................................................................................
Tcs Transmitter 0 Enable (t0en)—bit 0195................................................................................................................................................................
Tcs Transmitter 1 Enable (t1en)—bit 1195................................................................................................................................................................
Tcs Transmitter Word Length Control (twl[1:0])—bits196................................................................................................................................................................
Tcs Transmitter 2 Enable (t2en)—bit 2196................................................................................................................................................................
Tcs Transmitter Master (tmst)—bit 3196................................................................................................................................................................
Tcs Transmitter Data Shift Direction (tdir)—bit 6196................................................................................................................................................................
Tcs Transmitter Left Right Selection (tlrs)—bit 7197................................................................................................................................................................
Tcs Transmitter Clock Polarity (tckp)—bit 8197................................................................................................................................................................
Tcs Transmitter Data Word Expansion (tdwe)—bit198................................................................................................................................................................
Tcs Transmitter Relative Timing (trel)—bit 9198................................................................................................................................................................
Tcs Transmitter Interrupt Enable (txie)—bit 11199................................................................................................................................................................
Tcs Transmitter Interrupt Location (txil)—bit 12200................................................................................................................................................................
Tcs Reserved Bit—bit 13200................................................................................................................................................................
Tcs Transmitter Left Data Empty (tlde)—bit 14200................................................................................................................................................................
Tcs Transmitter Right Data Empty (trde)—bit 15201................................................................................................................................................................
Sai Transmit Data Registers (tx2, Tx1 And Tx0)201................................................................................................................................................................
Programming Considerations202................................................................................................................................................................
Sai Operation During Stop202................................................................................................................................................................
Initiating A Transmit Session202................................................................................................................................................................
Using A Single Interrupt To Service Both Receiver And Transmitter202................................................................................................................................................................
Sai State Machine203................................................................................................................................................................
Gpio Programming Model206................................................................................................................................................................
Gpio Register (gpior)206................................................................................................................................................................
Dax Signals214................................................................................................................................................................
Dax Functional Overview215................................................................................................................................................................
Dax Programming Model216................................................................................................................................................................
Dax Internal Architecture216................................................................................................................................................................
Dax Audio Data Registers A And B (xadra/xadrb)217................................................................................................................................................................
Dax Audio Data Buffer (xadbuf)217................................................................................................................................................................
Dax Audio Data Shift Register (xadsr)218................................................................................................................................................................
Dax Control Register (xctr)218................................................................................................................................................................
Dax Enable (xen)—bit 0218................................................................................................................................................................
Dax Interrupt Enable (xien)—bit 1218................................................................................................................................................................
Dax Stop Control (xstp)—bit 2218................................................................................................................................................................
Dax Clock Input Select (xcs[1:0])—bits 3–4219................................................................................................................................................................
Xctr Reserved Bits—bits 5-9, 16-23219................................................................................................................................................................
Dax Channel A Validity (xva)—bit 10219................................................................................................................................................................
Dax Channel A User Data (xua)—bit 11219................................................................................................................................................................
Dax Channel A Channel Status (xca)—bit 12219................................................................................................................................................................
Dax Channel B Validity (xvb)—bit 13219................................................................................................................................................................
Dax Channel B User Data (xub)—bit 14220................................................................................................................................................................
Dax Channel B Channel Status (xcb)—bit 15220................................................................................................................................................................
Dax Status Register (xstr)220................................................................................................................................................................
Dax Audio Data Register Empty (xade)—bit 0220................................................................................................................................................................
Xstr Reserved Bits—bits 1, 5–23220................................................................................................................................................................
Dax Transmit Underrun Error Flag (xaur)—bit 2220................................................................................................................................................................
Dax Block Transfer Flag (xblk)—bit 3221................................................................................................................................................................
Dax Transmit In Progress (xtip)—bit 4221................................................................................................................................................................
Dax Non-audio Data Buffer (xnadbuf)222................................................................................................................................................................
Dax Parity Generator (prtyg)222................................................................................................................................................................
Dax Biphase Encoder222................................................................................................................................................................
Dax Preamble Generator222................................................................................................................................................................
Dax Clock Multiplexer223................................................................................................................................................................
Dax State Machine224................................................................................................................................................................
Dax Programming Considerations224................................................................................................................................................................
Transmit Register Empty Interrupt Handling224................................................................................................................................................................
Block Transferred Interrupt Handling224................................................................................................................................................................
Dax Operation During Stop225................................................................................................................................................................
A.1 Introduction228................................................................................................................................................................
A.2 Bootstrapping The Dsp228................................................................................................................................................................
A.3 Bootstrap Program Listing228................................................................................................................................................................
B.1 Introduction234................................................................................................................................................................
B.2 Peripheral Addresses234................................................................................................................................................................
B.3 Interrupt Addresses234................................................................................................................................................................
B.4 Interrupt Priorities234................................................................................................................................................................
B.5 Instruction Set Summary234................................................................................................................................................................
B.6 Programming Sheets234................................................................................................................................................................

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