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Motorola DSP56012 User Manual

Motorola DSP56012 User Manual (270 pages)

24-Bit Digital Signal Processor  
Brand: Motorola | Category: Stereo System | Size: 2.31 MB
Table of contents
Table Of Contents3................................................................................................................................................................
List Of Figures13................................................................................................................................................................
Introduction23................................................................................................................................................................
Manual Organization24................................................................................................................................................................
Manual Conventions25................................................................................................................................................................
Dsp56012 Features26................................................................................................................................................................
Table 1-1 High True / Low True Signal Conventions26................................................................................................................................................................
Table 1-2 Dsp56012 Internal Memory Configurations27................................................................................................................................................................
Dsp56012 Architectural Overview28................................................................................................................................................................
Figure 1-1 Dsp56012 Block Diagram29................................................................................................................................................................
Peripheral Modules30................................................................................................................................................................
Dsp Core Processor30................................................................................................................................................................
Data Arithmetic And Logic Unit (data Alu)31................................................................................................................................................................
Address Generation Unit (agu)31................................................................................................................................................................
Program Control Unit32................................................................................................................................................................
Data Buses32................................................................................................................................................................
Address Buses32................................................................................................................................................................
Phase Lock Loop (pll)32................................................................................................................................................................
On-chip Emulation (once) Port33................................................................................................................................................................
Memories33................................................................................................................................................................
Program Memory33................................................................................................................................................................
Table 1-3 Interrupt Starting Addresses And Sources33................................................................................................................................................................
Data Memory35................................................................................................................................................................
Y Data Memory35................................................................................................................................................................
On-chip Memory Configuration Bits35................................................................................................................................................................
Table 1-4 Internal Memory Configurations35................................................................................................................................................................
Memory Configuration Bits36................................................................................................................................................................
External Memory36................................................................................................................................................................
Bootstrap Rom36................................................................................................................................................................
Reserved Memory Spaces36................................................................................................................................................................
Input/output36................................................................................................................................................................
Table 1-5 On-chip Peripheral Memory Map37................................................................................................................................................................
Parallel Host Interface (hi)38................................................................................................................................................................
Serial Host Interface (shi)38................................................................................................................................................................
Serial Audio Interface (sai)39................................................................................................................................................................
General Purpose I/o39................................................................................................................................................................
Digital Audio Transmitter (dax)39................................................................................................................................................................
Signal Groupings43................................................................................................................................................................
Table 2-1 Dsp56012 Functional Signal Groupings43................................................................................................................................................................
Figure 2-1 Dsp56012 Signals44................................................................................................................................................................
Power45................................................................................................................................................................
Table 2-2 Power Inputs45................................................................................................................................................................
Ground46................................................................................................................................................................
Table 2-3 Grounds46................................................................................................................................................................
Table 2-4 Phase Lock Loop Signals47................................................................................................................................................................
Interrupt And Mode Control48................................................................................................................................................................
Motorola48................................................................................................................................................................
Table 2-5 Interrupt And Mode Control48................................................................................................................................................................
Host Interface (hi)50................................................................................................................................................................
Table 2-6 Host Interface50................................................................................................................................................................
Table 2-7 Serial Host Interface (shi) Signals53................................................................................................................................................................
Sai Receive Section56................................................................................................................................................................
Table 2-8 Serial Audio Interface (sai) Receive Signals56................................................................................................................................................................
Sai Transmit Section57................................................................................................................................................................
Table 2-9 Serial Audio Interface (sai) Transmit Signals57................................................................................................................................................................
General Purpose Input/output (gpio)58................................................................................................................................................................
Digital Audio Interface (dax)58................................................................................................................................................................
Table 2-10 General Purpose I/o (gpio) Signals58................................................................................................................................................................
Table 2-11 Digital Audio Interface (dax) Signals58................................................................................................................................................................
Once Port59................................................................................................................................................................
Table 2-12 On-chip Emulation Port (once) Signals59................................................................................................................................................................
Dsp56012 Data And Program Memory63................................................................................................................................................................
Table 3-1 Internal Memory Configurations63................................................................................................................................................................
Memory, Operating Modes, And Interrupts63................................................................................................................................................................
And Y Data Rom64................................................................................................................................................................
Dsp56012 Data And Program Memory Maps64................................................................................................................................................................
Dynamic Switch Of Memory Configurations68................................................................................................................................................................
Internal I/o Memory Map70................................................................................................................................................................
Table 3-2 Internal I/o Memory Map70................................................................................................................................................................
Operating Mode Register (omr)72................................................................................................................................................................
Dsp Operating Mode (mc, Mb, Ma)-bits 4, 1, And 072................................................................................................................................................................
Program Ram Enable A And Program Ram Enable B72................................................................................................................................................................
Program Ram Enable A And Program Ram Enable B (pea And Peb)-bits 2 And72................................................................................................................................................................
Stop Delay (sd)-bit 672................................................................................................................................................................
Figure 3-5 Operating Mode Register (omr)72................................................................................................................................................................
Program Ram Enable A (pea)-bit 272................................................................................................................................................................
Program Ram Enable B (peb)-bit 372................................................................................................................................................................
Operating Modes73................................................................................................................................................................
Table 3-3 Operating Modes73................................................................................................................................................................
Interrupt Priority Register75................................................................................................................................................................
Figure 3-6 Interrupt Priority Register (addr X:$ffff)76................................................................................................................................................................
Table 3-4 Interrupt Priorities76................................................................................................................................................................
Table 3-5 Interrupt Vectors77................................................................................................................................................................
Phase Lock Loop (pll) Configuration79................................................................................................................................................................
Operation On Hardware Reset80................................................................................................................................................................
Figure 3-7 Pll Configuration80................................................................................................................................................................
Port B Configuration83................................................................................................................................................................
Figure 4-1 Port B Interface83................................................................................................................................................................
Figure 4-2 Parallel Port B Registers84................................................................................................................................................................
Figure 4-3 Port B Gpio Signals And Registers85................................................................................................................................................................
Port B Control (pbc) Register86................................................................................................................................................................
Figure 4-4 Port B I/o Pin Control Logic86................................................................................................................................................................
Port B Data Direction Register (pbddr)87................................................................................................................................................................
Port B Data (pbd) Register87................................................................................................................................................................
Programming The Gpio88................................................................................................................................................................
Figure 4-5 Instructions To Write/read Parallel Data With Port B88................................................................................................................................................................
Figure 4-6 I/o Port B Configuration89................................................................................................................................................................
Hi Features90................................................................................................................................................................
Hi Block Diagram91................................................................................................................................................................
Hi-dsp Viewpoint92................................................................................................................................................................
Figure 4-7 Hi Block Diagram92................................................................................................................................................................
Programming Model-dsp Viewpoint93................................................................................................................................................................
Hi Control Register (hcr)94................................................................................................................................................................
Figure 4-8 Hi Programming Model-dsp Viewpoint94................................................................................................................................................................
Hcr Hi Receive Interrupt Enable (hrie)-bit 095................................................................................................................................................................
Hcr Hi Transmit Interrupt Enable (htie)-bit 195................................................................................................................................................................
Hcr Hi Command Interrupt Enable (hcie)-bit 295................................................................................................................................................................
Hcr Hi Flag 2 (hf2)-bit 395................................................................................................................................................................
Hcr Hi Flag 3 (hf3)-bit 495................................................................................................................................................................
Hcr Reserved-bits 5, 6, And 796................................................................................................................................................................
Hi Status Register (hsr)96................................................................................................................................................................
Hsr Hi Receive Data Full (hrdf)-bit 096................................................................................................................................................................
Hsr Hi Transmit Data Empty (htde)-bit 196................................................................................................................................................................
Hsr Hi Command Pending (hcp)-bit 297................................................................................................................................................................
Hsr Hi Flag 1 (hf1)-bit 497................................................................................................................................................................
Hsr Reserved-bits 5 And 698................................................................................................................................................................
Hsr Dma Status (dma)-bit 798................................................................................................................................................................
Hi Receive Data Register (horx)98................................................................................................................................................................
Figure 4-9 Hi Flag Operation98................................................................................................................................................................
Hi Transmit Data Register (hotx)99................................................................................................................................................................
Register Contents After Reset99................................................................................................................................................................
Table 4-1 Hi Registers After Reset-dsp Cpu Side99................................................................................................................................................................
Dsp Interrupts100................................................................................................................................................................
Hi Usage Considerations-dsp Side101................................................................................................................................................................
Hi-host Processor Viewpoint101................................................................................................................................................................
Programming Model-host Processor Viewpoint101................................................................................................................................................................
Host Command102................................................................................................................................................................
Figure 4-10 Host Processor Programming Model-host Side103................................................................................................................................................................
Interrupt Control Register (icr)104................................................................................................................................................................
Icr Receive Request Enable (rreq)-bit 0104................................................................................................................................................................
Icr Transmit Request Enable (treq)-bit 1104................................................................................................................................................................
Figure 4-11 Hi Register Map104................................................................................................................................................................
Icr Reserved-bit 2105................................................................................................................................................................
Icr Hi Flag 0 (hf0)-bit 3105................................................................................................................................................................
Table 4-2 Horeq Pin Definition105................................................................................................................................................................
Icr Hi Flag 1 (hf1)-bit 4106................................................................................................................................................................
Icr Hi Mode Control (hm1 And Hm0)-bits 5 And 6106................................................................................................................................................................
Figure 4-12 Hsr And Hcr Operation106................................................................................................................................................................
Table 4-3 Hi Mode Bit Definition106................................................................................................................................................................
Icr Initialize Bit (init)-bit 7107................................................................................................................................................................
Hi Initialization107................................................................................................................................................................
Table 4-4 Horeq Pin Definition108................................................................................................................................................................
Command Vector Register (cvr)109................................................................................................................................................................
Cvr Hi Vector (hv)-bits 0-5109................................................................................................................................................................
Figure 4-13 Command Vector Register109................................................................................................................................................................
Cvr Reserved-bit 6110................................................................................................................................................................
Cvr Host Command (hc)-bit 7110................................................................................................................................................................
Interrupt Status Register (isr)110................................................................................................................................................................
Isr Receive Data Register Full (rxdf)-bit 0110................................................................................................................................................................
Isr Transmit Data Register Empty (txde)-bit 1111................................................................................................................................................................
Isr Transmitter Ready (trdy)-bit 2111................................................................................................................................................................
Isr Hi Flag 2 (hf2)-bit 3 (read Only)111................................................................................................................................................................
Isr Hi Flag 3 (hf3)-bit 4 (read Only)111................................................................................................................................................................
Isr Reserved-bit 5111................................................................................................................................................................
Isr Host Request (horeq)-bit 7112................................................................................................................................................................
Interrupt Vector Register (ivr)112................................................................................................................................................................
Receive Byte Registers (rxh, Rxm, Rxl)112................................................................................................................................................................
Transmit Byte Registers (txh, Txm, Txl)113................................................................................................................................................................
Registers After Reset113................................................................................................................................................................
Table 4-5 Hi Registers After Reset (host Side)114................................................................................................................................................................
Hi Signals115................................................................................................................................................................
Hi Data Bus (h0-h7)115................................................................................................................................................................
Hi Address (hoa2-hoa0)115................................................................................................................................................................
Hi Read/write (hr/w)115................................................................................................................................................................
Hi Enable (hen)115................................................................................................................................................................
Host Request (horeq)115................................................................................................................................................................
Host Acknowledge (hack)116................................................................................................................................................................
Table 4-6 Port B Pin Definitions116................................................................................................................................................................
Servicing The Hi117................................................................................................................................................................
Hi-host Processor Data Transfer117................................................................................................................................................................
Figure 4-14 Host Processor Transfer Timing117................................................................................................................................................................
Host Interrupts Using Host Request (horeq)118................................................................................................................................................................
Polling118................................................................................................................................................................
Servicing Non-dma Interrupts119................................................................................................................................................................
Figure 4-15 Interrupt Vector Register Read Timing120................................................................................................................................................................
Figure 4-16 Hi Interrupt Structure120................................................................................................................................................................
Servicing Dma Interrupts121................................................................................................................................................................
Figure 4-17 Dma Transfer Logic And Timing121................................................................................................................................................................
Host Interface Application Examples122................................................................................................................................................................
Figure 4-18 Hi Initialization Flowchart122................................................................................................................................................................
Figure 4-19 Hi Initialization-dsp Side123................................................................................................................................................................
Figure 4-20 Hi Initialization-host Side, Interrupt Mode124................................................................................................................................................................
Polling/interrupt Controlled Data Transfer125................................................................................................................................................................
Figure 4-21 Hi Mode And Init Bits125................................................................................................................................................................
Figure 4-22 Hi Initialization-host Side, Polling Mode126................................................................................................................................................................
Figure 4-23 Hi Configuration-host Side126................................................................................................................................................................
Figure 4-24 Hi Initialization-host Side, Dma Mode127................................................................................................................................................................
Host To Dsp-data Transfer129................................................................................................................................................................
Host To Dsp-command Vector131................................................................................................................................................................
Figure 4-28 Receive Data From Host-main Program133................................................................................................................................................................
Figure 4-29 Receive Data From Host Interrupt Routine133................................................................................................................................................................
Host To Dsp-bootstrap Loading Using The Hi134................................................................................................................................................................
Figure 4-30 Transmit/receive Byte Registers134................................................................................................................................................................
Figure 4-31 Bootstrap Using The Host Interface135................................................................................................................................................................
Dsp To Host-data Transfer136................................................................................................................................................................
Dma Data Transfer139................................................................................................................................................................
Figure 4-34 Main Program: Transmit 24-bit Data To Host139................................................................................................................................................................
Figure 4-35 Hi Hardware-dma Mode140................................................................................................................................................................
Host To Dsp-internal Processing141................................................................................................................................................................
Figure 4-36 Dma Transfer And Hi Interrupts141................................................................................................................................................................
Host To Dsp-dma Procedure142................................................................................................................................................................
Dsp To Hi -internal Processing144................................................................................................................................................................
Dsp To Host-dma Procedure145................................................................................................................................................................
Hi Port Usage Considerations-host Side145................................................................................................................................................................
Overwriting Transmit Byte Registers146................................................................................................................................................................
Synchronization Of Status Bits From Dsp To Host146................................................................................................................................................................
Overwriting The Host Vector146................................................................................................................................................................
Cancelling A Pending Host Command Interrupt146................................................................................................................................................................
Coordinating Data Transfers147................................................................................................................................................................
Unused Pins147................................................................................................................................................................
Serial Host Interface Internal Architecture152................................................................................................................................................................
Figure 5-1 Serial Host Interface Block Diagram152................................................................................................................................................................
Shi Clock Generator153................................................................................................................................................................
Serial Host Interface Programming Model153................................................................................................................................................................
Figure 5-2 Shi Clock Generator153................................................................................................................................................................
Figure 5-3 Shi Programming Model-host Side153................................................................................................................................................................
Table 5-1 Shi Interrupt Vectors155................................................................................................................................................................
Table 5-2 Shi Internal Interrupt Priorities155................................................................................................................................................................
Shi Input/output Shift Register (iosr)-host Side156................................................................................................................................................................
Shi Host Transmit Data Register (htx)-dsp Side156................................................................................................................................................................
Figure 5-5 Shi I/o Shift Register (iosr)156................................................................................................................................................................
Shi Host Receive Data Fifo (hrx)-dsp Side157................................................................................................................................................................
Shi Slave Address Register (hsar)-dsp Side157................................................................................................................................................................
Hsar Reserved Bits-bits 17-0,19157................................................................................................................................................................
Shi Clock Control Register (hckr)-dsp Side157................................................................................................................................................................
Clock Phase And Polarity (cpha And Cpol)-bits158................................................................................................................................................................
Figure 5-6 Spi Data-to-clock Timing Diagram158................................................................................................................................................................
Hckr Prescaler Rate Select (hrs)-bit 2159................................................................................................................................................................
Hckr Divider Modulus Select (hdm[5:0])-bits 8-3160................................................................................................................................................................
Hckr Reserved Bits-bits 23-14, 11-9160................................................................................................................................................................
Hckr Filter Mode (hfm[1:0]) - Bits 13-12160................................................................................................................................................................
Table 5-3 Shi Noise Reduction Filter Mode160................................................................................................................................................................
Shi Control/status Register (hcsr)-dsp Side161................................................................................................................................................................
Hcsr Host Enable (hen)-bit 0161................................................................................................................................................................
Shi Individual Reset161................................................................................................................................................................
Hcsr I161................................................................................................................................................................
Hcsr Serial Host Interface Mode (hm[1:0])-bits162................................................................................................................................................................
Hcsr Reserved Bits-bits 23, 18, 16, And 4162................................................................................................................................................................
Hcsr Fifo-enable Control (hfifo)-bit 5162................................................................................................................................................................
Hcsr Master Mode (hmst)-bit 6162................................................................................................................................................................
Table 5-4 Shi Data Size162................................................................................................................................................................
Hcsr Host-request Enable (hrqe[1:0])-bits 8-7163................................................................................................................................................................
Hcsr Idle (hidle)-bit 9163................................................................................................................................................................
Table 5-5 Hreq Function In Shi Slave Modes163................................................................................................................................................................
Hcsr Bus-error Interrupt Enable (hbie)-bit 10164................................................................................................................................................................
Hcsr Transmit-interrupt Enable (htie)-bit 11164................................................................................................................................................................
Hcsr Receive Interrupt Enable (hrie[1:0])-bits164................................................................................................................................................................
Hcsr Host Transmit Underrun Error (htue)-bit 14165................................................................................................................................................................
Hcsr Host Transmit Data Empty (htde)-bit 15165................................................................................................................................................................
Table 5-6 Hcsr Receive Interrupt Enable Bits165................................................................................................................................................................
Host Receive Overrun Error (hroe)-bit 20166................................................................................................................................................................
Host Bus Error (hber)-bit 21166................................................................................................................................................................
Hcsr Host Busy (hbusy)—bit 22167................................................................................................................................................................
Characteristics Of The Spi Bus167................................................................................................................................................................
Characteristics Of The I168................................................................................................................................................................
Overview168................................................................................................................................................................
Characteristics Of The I2c Bus168................................................................................................................................................................
Figure 5-8 I 2 C Start And Stop Events169................................................................................................................................................................
Figure 5-9 Acknowledgment On The I169................................................................................................................................................................
C Data Transfer Formats170................................................................................................................................................................
Figure 5-10 I170................................................................................................................................................................
Figure 5-11 I170................................................................................................................................................................
Shi Programming Considerations171................................................................................................................................................................
Spi Slave Mode171................................................................................................................................................................
Spi Master Mode172................................................................................................................................................................
I 2 C Slave Mode173................................................................................................................................................................
Receive Data In I 2 C Slave Mode174................................................................................................................................................................
Transmit Data In I 2 C Slave Mode175................................................................................................................................................................
C Master Mode175................................................................................................................................................................
Receive Data In I C Master Mode177................................................................................................................................................................
Transmit Data In I C Master Mode177................................................................................................................................................................
Shi Operation During Stop178................................................................................................................................................................
Serial Audio Interface Internal Architecture182................................................................................................................................................................
Baud-rate Generator182................................................................................................................................................................
Figure 6-1 Sai Baud-rate Generator Block Diagram182................................................................................................................................................................
Receive Section Overview183................................................................................................................................................................
Figure 6-2 Sai Receive Section Block Diagram183................................................................................................................................................................
Sai Transmit Section Overview184................................................................................................................................................................
Figure 6-3 Sai Transmit Section Block Diagram185................................................................................................................................................................
Serial Audio Interface Programming Model186................................................................................................................................................................
Figure 6-4 Sai Registers186................................................................................................................................................................
Baud Rate Control Register (brc)187................................................................................................................................................................
Table 6-1 Sai Interrupt Vector Locations187................................................................................................................................................................
Table 6-2 Sai Internal Interrupt Priorities187................................................................................................................................................................
Prescale Modulus Select (pm[7:0])-bits 7-0188................................................................................................................................................................
Prescaler Range (psr)-bit 8188................................................................................................................................................................
Brc Reserved Bits-bits 15-9188................................................................................................................................................................
Receiver Control/status Register (rcs)188................................................................................................................................................................
Rcs Receiver 0 Enable (r0en)-bit 0188................................................................................................................................................................
Rcs Receiver 1 Enable (r1en)-bit 1189................................................................................................................................................................
Rcs Reserved Bit-bits 13 And 2189................................................................................................................................................................
Rcs Receiver Word Length Control (rwl[1:0])-bits 4 And 5189................................................................................................................................................................
Table 6-3 Receiver Word Length Control189................................................................................................................................................................
Rcs Receiver Data Shift Direction (rdir)-bit 6190................................................................................................................................................................
Rcs Receiver Left Right Selection (rlrs)-bit 7190................................................................................................................................................................
Figure 6-5 Receiver Data Shift Direction (rdir) Programming190................................................................................................................................................................
Figure 6-6 Receiver Left/right Selection (rlrs) Programming190................................................................................................................................................................
Rcs Receiver Clock Polarity (rckp)-bit 8191................................................................................................................................................................
Rcs Receiver Relative Timing (rrel)-bit 9191................................................................................................................................................................
Figure 6-7 Receiver Clock Polarity (rckp) Programming191................................................................................................................................................................
Rcs Receiver Data Word Truncation (rdwt)-bit 10192................................................................................................................................................................
Figure 6-8 Receiver Relative Timing (rrel) Programming192................................................................................................................................................................
Figure 6-9 Receiver Data Word Truncation (rdwt) Programming192................................................................................................................................................................
Rcs Receiver Interrupt Enable (rxie)-bit 11193................................................................................................................................................................
Rcs Receiver Interrupt Location (rxil)-bit 12193................................................................................................................................................................
Rcs Receiver Left Data Full (rldf)-bit 14194................................................................................................................................................................
Rcs Receiver Right Data Full (rrdf)-bit 15194................................................................................................................................................................
Sai Receive Data Registers (rx0 And Rx1)195................................................................................................................................................................
Transmitter Control/status Register (tcs)195................................................................................................................................................................
Tcs Transmitter 0 Enable (t0en)-bit 0195................................................................................................................................................................
Tcs Transmitter 1 Enable (t1en)-bit 1195................................................................................................................................................................
Tcs Transmitter Master (tmst)-bit 3196................................................................................................................................................................
Tcs Transmitter Word Length Control (twl[1:0])-bits 4 & 5196................................................................................................................................................................
Tcs Transmitter Data Shift Direction (tdir)-bit 6196................................................................................................................................................................
Table 6-4 Transmitter Word Length196................................................................................................................................................................
Tcs Transmitter Left Right Selection (tlrs)-bit 7197................................................................................................................................................................
Figure 6-10 Transmitter Data Shift Direction (tdir) Programming197................................................................................................................................................................
Figure 6-11 Transmitter Left/right Selection (tlrs) Programming197................................................................................................................................................................
Tcs Transmitter Relative Timing (trel)-bit 9198................................................................................................................................................................
Tcs Transmitter Data Word Expansion (tdwe)-bit 10198................................................................................................................................................................
Figure 6-12 Transmitter Clock Polarity (tckp) Programming198................................................................................................................................................................
Figure 6-13 Transmitter Relative Timing (trel) Programming198................................................................................................................................................................
Figure 6-14 Transmitter Data Word Expansion (tdwe) Programming199................................................................................................................................................................
Tcs Transmitter Interrupt Enable (txie)—bit 11199................................................................................................................................................................
Tcs Transmitter Interrupt Location (txil)-bit 12200................................................................................................................................................................
Tcs Reserved Bit—bit 13200................................................................................................................................................................
Tcs Transmitter Left Data Empty (tlde)-bit 14200................................................................................................................................................................
Tcs Transmitter Right Data Empty (trde)-bit 15201................................................................................................................................................................
Sai Transmit Data Registers (tx2, Tx1 And Tx0)201................................................................................................................................................................
Programming Considerations202................................................................................................................................................................
Sai Operation During Stop202................................................................................................................................................................
Initiating A Transmit Session202................................................................................................................................................................
Using A Single Interrupt To Service Both Receiver And202................................................................................................................................................................
Sai State Machine203................................................................................................................................................................
Gpio Programming Model207................................................................................................................................................................
Figure 7-1 Gpio Control/data Register207................................................................................................................................................................
Gpior Data Bits (gd[7:0])-bits 7-0208................................................................................................................................................................
Gpior Data Direction Bits (gdd[7:0])-bits 15-8208................................................................................................................................................................
Gpior Control Bits (gc[7:0])-bits 23-16208................................................................................................................................................................
Table 7-1 Gpio Pin Configuration208................................................................................................................................................................
Figure 7-2 Gpio Circuit Diagram209................................................................................................................................................................
Dax Signals214................................................................................................................................................................
Figure 8-1 Digital Audio Transmitter (dax) Block Diagram214................................................................................................................................................................
Dax Functional Overview215................................................................................................................................................................
Dax Programming Model216................................................................................................................................................................
Dax Internal Architecture216................................................................................................................................................................
Table 8-1 Dax Interrupt Vectors216................................................................................................................................................................
Table 8-2 Dax Interrupt Priority216................................................................................................................................................................
Dax Audio Data Registers A And B (xadra/xadrb)217................................................................................................................................................................
Dax Audio Data Buffer (xadbuf)217................................................................................................................................................................
Figure 8-2 Dax Programming Mode217................................................................................................................................................................
Dax Audio Data Shift Register (xadsr)218................................................................................................................................................................
Dax Control Register (xctr)218................................................................................................................................................................
Dax Enable (xen)-bit 0218................................................................................................................................................................
Dax Interrupt Enable (xien)-bit 1218................................................................................................................................................................
Dax Stop Control (xstp)-bit 2218................................................................................................................................................................
Dax Clock Input Select (xcs[1:0])-bits 3-4219................................................................................................................................................................
Xctr Reserved Bits-bits 5-9, 16-23219................................................................................................................................................................
Dax Channel A Validity (xva)-bit 10219................................................................................................................................................................
Dax Channel A User Data (xua)-bit 11219................................................................................................................................................................
Dax Channel A Channel Status (xca)-bit 12219................................................................................................................................................................
Dax Channel B Validity (xvb)-bit 13219................................................................................................................................................................
Table 8-3 Clock Source Selection219................................................................................................................................................................
Dax Channel B User Data (xub)-bit 14220................................................................................................................................................................
Dax Channel B Channel Status (xcb)-bit 15220................................................................................................................................................................
Dax Status Register (xstr)220................................................................................................................................................................
Dax Audio Data Register Empty (xade)—bit 0220................................................................................................................................................................
Xstr Reserved Bits-bits 1, 5-23220................................................................................................................................................................
Dax Transmit Underrun Error Flag (xaur)-bit 2220................................................................................................................................................................
Dax Block Transfer Flag (xblk)-bit 3221................................................................................................................................................................
Dax Transmit In Progress (xtip)-bit 4221................................................................................................................................................................
Figure 8-3 Dax Relative Timing221................................................................................................................................................................
Dax Non-audio Data Buffer (xnadbuf)222................................................................................................................................................................
Dax Parity Generator (prtyg)222................................................................................................................................................................
Dax Biphase Encoder222................................................................................................................................................................
Dax Preamble Generator222................................................................................................................................................................
Table 8-4 Preamble Bit Patterns222................................................................................................................................................................
Dax Clock Multiplexer223................................................................................................................................................................
Figure 8-4 Preamble Sequence223................................................................................................................................................................
Figure 8-5 Clock Multiplexer Diagram223................................................................................................................................................................
Dax State Machine224................................................................................................................................................................
Dax Programming Considerations224................................................................................................................................................................
Transmit Register Empty Interrupt Handling224................................................................................................................................................................
Block Transferred Interrupt Handling224................................................................................................................................................................
Dax Operation During Stop225................................................................................................................................................................
Bootstrapping The Dsp228................................................................................................................................................................
Bootstrap Program Listing228................................................................................................................................................................
A.1 Introduction228................................................................................................................................................................
A.2 Bootstrapping The Dsp228................................................................................................................................................................
A.3 Bootstrap Program Listing228................................................................................................................................................................
B.1 Introduction234................................................................................................................................................................
B.2 Peripheral Addresses234................................................................................................................................................................
B.3 Interrupt Addresses234................................................................................................................................................................
B.4 Interrupt Priorities234................................................................................................................................................................
B.5 Instruction Set Summary234................................................................................................................................................................
B.6 Programming Sheets234................................................................................................................................................................
Peripheral Addresses235................................................................................................................................................................
Interrupt Addresses235................................................................................................................................................................
Interrupt Priorities235................................................................................................................................................................
Instruction Set Summary235................................................................................................................................................................
Programming Sheets235................................................................................................................................................................
Figure B-1 On-chip Peripheral Memory Map236................................................................................................................................................................
Table B-1 Interrupt Starting Addresses And Sources237................................................................................................................................................................

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