Ccop Linear Feedback Shift Register (Cfsrz); Ccop Feedback Tap Register (Cfbtz); Ccop Feedforward Tap Register (Cfftz); Ccop Bit Select Register (Cbsrz) - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
All of the registers may be used in the Cipher modes, but in the Parity Coding modes
only the first (set A, in Parity Coding Using One CFSR) or the first and second (sets A
and B, in Parity Coding Using Two Concatenated CFSRs) sets are enabled.
14.4.5.1

CCOP Linear Feedback Shift Register (CFSRz)

The CCOP Linear Feedback Shift Register (CFSRz) is a 24-bit read/write shift register,
which manipulates input data according to the feedback taps configuration. Input data
can be shifted in serially while it is connected to the left-end or to the right-end of the
CFSR. The input can also be gated (zero) for certain periods of the CCOP processing so
that data shifted into the CFSR is derived exclusively from its feedback taps. Data shift is
always from left to right. CFSRz is cleared by hardware, software or CCOP individual
reset.
14.4.5.2

CCOP FeedBack Tap Register (CFBTz)

The CCOP FeedBack Tap Register (CFBTz) is the first 24-bit read/write register which
configures the operation of CFSRz. In the Cipher modes, this register specifies the
position of the feedback taps (XOR gates) in CFSRz. In the Parity Coding modes, this
register specifies the position of the XOR gates between adjacent bits of CFSRz
connected to the feedback taps.
14.4.5.3

CCOP FeedForward Tap Register (CFFTz)

The CCOP FeedForward Tap Register (CFFTz) is the second 24-bit read/write register
which configures the operation of CFSRz. In the Cipher modes, this register specifies the
position of the feedforward taps in CFSRz, from which the output data is derived. In the
Parity Coding modes, this register specifies the position of the XOR gates between
adjacent bits of CFSRz connected to the input bit.
14.4.5.4

CCOP Bit Select Register (CBSRz)

The CCOP Bit Select Register (CBSRz) is the third 24-bit read/write register which
configures the operation of CFSRz. In the Cipher modes, this register specifies which bits
from CFSRz will be selected for use by the Bitwise Majority function. In the Parity
Coding modes, this register specifies which bits from CFSRz will be selected for the Zero
Detect function.
14.4.5.5

CCOP Mask Register (CMSKz)

The CCOP Mask Register (CMSKz) is the fourth 24-bit read/write register which
configures the operation of CFSRz. In the Cipher modes, this register defines which of
the bits determined by CBSRz will be XORed with one (inverted) before it goes to the
Bitwise Majority function. In the Parity Coding modes, this register selects which bit in
CFSRz drives the feedback line. In the Parity Coding modes, CMSKz should have only
one bit set, specifying the CFSR bit from which the feedback line is driven (i.e. the degree
of the generator polynomial).
14-20 DSP56305 User's Manual MOTOROLA