Frame Sync Settings; Frame Sync Signal Format; Frame Sync Length For Multiple Devices; Word Length Frame Sync Position - Motorola DSP56305 User Manual

Enhanced Synchronous Serial Interface (ESSI)
Operating Modes
in these modes, receive and transmit may have different word and frame rates (but the
receive and transmit word size is always the same number of bits).
On the other hand, the transmit timing is always the same for all transmit channels, in all
modes of operation. All enabled ESSI transmitters (one in Synchronous mode, and up to
three in Asynchronous mode) will have the same bit, word, and frame timing.
7.5.3.5

Frame Sync Settings

The transmitter and receiver can operate independently. The transmitter can have either
a bit-long or word-long frame-sync signal format, and the receiver can have the same or
another format. The selection is made by programming FSL[1:0], FSR, and FSP bits in the
CRB.
7.5.3.5.1

Frame Sync Signal Format

FSL1 controls the frame-sync signal format.
• If the FSL1 bit is cleared, the RX frame sync is asserted during the entire data
transfer period. This frame sync length is compatible with Motorola codecs, serial
peripherals that conform to the Motorola SPI, serial A/D and D/A converters,
shift registers, and telecommunication Pulse Code Modulation (PCM) serial I/O.
• If the FSL1 bit is set, the RX frame sync pulses active for one bit clock immediately
before the data transfer period. This frame sync length is compatible with Intel
and National components, codecs, and telecommunication PCM serial I/O.
7.5.3.5.2

Frame Sync Length for Multiple Devices

The ability to mix frame sync lengths is useful in configuring systems in which data is
received from one type of device (e.g., codec) and transmitted to a different type of
device. FSL0 controls whether RX and TX have the same frame sync length.
• If the FSL0 bit is cleared, both RX and TX have the same frame sync length.
• If the FSL0 bit is set, RX and TX have different frame sync lengths.
FSL0 is ignored when the SYN bit is set.
7.5.3.5.3

Word Length Frame Sync Position

The FSR bit controls the relative timing of the word length frame sync relative to the data
word timing.
• When the FSR bit is cleared, the word length frame sync is generated (or
expected) with the first bit of the data word.
• When the FSR bit is set, the word length frame sync is generated (or expected)
with the last bit of the previous word.
FSR is ignored when a bit length frame sync is selected.
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