Figure 4-5 Identification Register Configuration; Xtal Disable (Xtld)—Pctl Bit 16; Predivider Factor Bits (Pd3:0)—Pctl Bits 20–23; Device Identification Register - Motorola DSP56305 User Manual

Core Configuration

Device Identification Register

4.8.3 XTAL Disable (XTLD)—PCTL Bit 16
The XTAL Disable bit (XTLD) controls the on-chip crystal oscillator XTAL output. The
XTLD bit is cleared during DSP56305 hardware reset, which means that the XTAL
output signal is active, permitting normal operation of the crystal oscillator.
4.8.4 PreDivider Factor Bits (PD3:0)—PCTL Bits 20–23
The PreDivider Factor bits (PD3:0) define the Predivider Factor (PDF) applied to the PLL
input frequency. The PD bits are cleared during DSP56305 hardware reset, which
corresponds to a PDF of one.
4.9 DEVICE IDENTIFICATION REGISTER
The Device Identification Register (IDR) is a 24-bit, read-only factory programmed
register which identifies DSP56300 family members. It specifies the derivative number
and revision number of the device. This information may be used in testing or by
software. Figure 4-5 gives the contents of the IDR for the DSP56305 Revision 0.
The IDR for a specific mask can be found on the silicon errata sheet on the Motorola DSP
Web page. Revision numbers are assigned as follows: $0 is revision 0, $1 is revision A, $2
is revision B, and so on. The derivative number is $305.
23
Reserved
00000000
Figure 4-5 Identification Register Configuration (DSP56305 Revision 0)
4-24
16 15 12
Revision Number
0000
DSP56305 User's Manual
11
Derivative Number
001100000101
0
AA1412
MOTOROLA