Motorola DSP56305 User Manual page 153

24-bit digital signal processor
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– UB Mode (cont.)
• Input data alignment of 16-bit words to 24-bit words
– left aligned and zero filled
– right aligned and zero extended
– right aligned and sign extended
• Data Buffers: FIFOs up to eight words deep, on both transmit and receive data
paths
• Handshaking Protocols
– Software polled
– Interrupt driven (fast or long)
– Direct Memory Access (up to four DSP56300 core DMA channels)
• GPIO
– 24 I/O signals (data and signal direction are programmable)
• Self Configuration
– DSP56300 core can indirectly access the CCMR, CLAT, and CBMA HI32
configuration registers
• Instructions
– Memory mapped registers allow standard MOVE instruction for data transfer
between DSP56305 and external hosts
– Special MOVEP instruction provides for I/O service capability using fast
interrupts, and provides faster execution with fewer instruction words
– Bit addressing instructions (e.g., BCHG, BCLR, BSET, BTST, JCLR, JSCLR,
JSET, JSSET) simplify I/O service routines.
MOTOROLA
DSP56305 User's Manual
HOST INTERFACE (HI32)
HI32 Features
6-5

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