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On-Chip Emulation Module
Trace Buffer
10.8.3
OnCE GDB Register (OGDBR)
The OnCE GDB Register (OGDBR) is a 16-bit latch that can only be read through the
JTAG port. The OGDBR is not actually required for restoring the pipeline status, but is
required as a means of passing information between the chip and the external command
controller. The OGDBR is mapped on the X internal I/O space at address $FFFC.
Whenever the external command controller needs the contents of a register or memory
location, it forces the chip to execute an instruction that brings that information to the
OGDBR. Then the contents of the OGDBR are delivered serially to the external
command controller by the command READ GDB REGISTER.
10.9
TRACE BUFFER
To ease debugging activity and keep track of program flow, the DSP56300 core provides
a number of on-chip dedicated resources. There are three read-only PAB registers that
give pipeline information when the Debug mode is entered, and a Trace buffer that
stores the address of the last instruction that was executed, as well as the addresses of
the last twelve change of flow instructions.
10.9.1
OnCE PAB Register for Fetch (OPABFR)
The OnCE PAB Register for Fetch Register (OPABFR) is a 16-bit register that stores the
address of the last instruction whose fetch was started before the Debug mode was
entered.The OPABFR can only be read through the JTAG port. This register is not
affected by the operations performed during the Debug mode.
10.9.2
PAB Register for Decode (OPABDR)
The OnCE PAB Register for Decode Register (OPABDR) is a 16-bit register that stores the
address of the instruction currently on the PDB. This is the instruction whose fetch was
completed before the chip has entered the Debug mode. The OPABDR can only be read
through the JTAG port. This register is not affected by the operations performed during
the Debug mode.
10-20
DSP56305 User's Manual
MOTOROLA
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