Pll And Clock Oscillator - Motorola DSP56305 User Manual

• VBA—Vector Base Address register
• SZ—Size register
• SP—Stack Pointer
• OMR—Operating Mode Register
• SC—Stack Counter register
The PCU also includes a hardware System Stack (SS).
1.6.4

PLL and Clock Oscillator

The clock generator in the DSP56300 core is composed of two main blocks: the PLL,
which performs clock input division, frequency multiplication, and skew elimination;
and the Clock Generator (CLKGEN), which performs low power division and clock
pulse generation.
• Allows change of low power Divide Factor (DF) without loss of lock
• Output clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a low
frequency clock input, offering two immediate benefits:
• A lower frequency clock input reduces the overall electromagnetic interference
generated by a system.
• The ability to oscillate at different frequencies reduces costs by eliminating the
need to add additional oscillators to a system.
1.6.5 JTAG Test Access Port and On-Chip Emulation (OnCE)
Module
The DSP56300 core provides a dedicated user-accessible Test Access Port (TAP) that is
fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture. Problems associated with testing high density circuit boards have led to
development of this standard under the sponsorship of the Test Technology Committee
of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core implementation
supports circuit-board test strategies based on this standard.
MOTOROLA DSP56305 User's Manual
DSP56305 Overview
DSP56300 Core Functional Blocks
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