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Motorola DSP56305 User Manual

Motorola DSP56305 User Manual (664 pages)

24-Bit  
Brand: Motorola | Category: Processor | Size: 5.47 MB
Table of contents
Table Of Contents3................................................................................................................................................................
Section 1 Dsp56305 Overview41................................................................................................................................................................
Introduction43................................................................................................................................................................
Manual Organization43................................................................................................................................................................
Manual Conventions45................................................................................................................................................................
Dsp56305 Features46................................................................................................................................................................
Dsp56305 Core Description47................................................................................................................................................................
General Features47................................................................................................................................................................
Hardware Debugging Support47................................................................................................................................................................
Reduced Power Dissipation47................................................................................................................................................................
Dsp56300 Core Functional Blocks48................................................................................................................................................................
Data Alu48................................................................................................................................................................
Data Alu Registers48................................................................................................................................................................
Multiplier-accumulator (mac)49................................................................................................................................................................
Address Generation Unit (agu)49................................................................................................................................................................
Program Control Unit (pcu)50................................................................................................................................................................
Pll And Clock Oscillator51................................................................................................................................................................
On-chip Memory52................................................................................................................................................................
Off-chip Memory Expansion53................................................................................................................................................................
Internal Buses53................................................................................................................................................................
Dsp56305 Block Diagram54................................................................................................................................................................
Figure 1-1 Dsp56305 Block Diagram54................................................................................................................................................................
Direct Memory Access (dma)55................................................................................................................................................................
Dsp56305 Architecture Overview55................................................................................................................................................................
General Purpose I/o (gpio) Functionality55................................................................................................................................................................
Host Interface (hi32)56................................................................................................................................................................
Enhanced Synchronous Serial Interface (essi)56................................................................................................................................................................
Serial Communications Interface (sci)57................................................................................................................................................................
Timer/event Counter (tec)57................................................................................................................................................................
Section 2 Signal/connection Descriptions59................................................................................................................................................................
Signal Groupings61................................................................................................................................................................
Figure 2-1 Signals Identified By Functional Group62................................................................................................................................................................
Figure 2-2 Host Interface/port B Detail Signal Diagram63................................................................................................................................................................
Power64................................................................................................................................................................
Ground65................................................................................................................................................................
Clock66................................................................................................................................................................
Phase Lock Loop (pll)66................................................................................................................................................................
External Memory Expansion Port (port A)67................................................................................................................................................................
External Address Bus68................................................................................................................................................................
External Data Bus68................................................................................................................................................................
External Bus Control69................................................................................................................................................................
Interrupt And Mode Control73................................................................................................................................................................
Host Port Configuration76................................................................................................................................................................
Serial Communication Interface (sci)93................................................................................................................................................................
Timers94................................................................................................................................................................
Jtag/once Interface96................................................................................................................................................................
Section 3 Memory Configuration99................................................................................................................................................................
Memory Spaces101................................................................................................................................................................
Program Memory Space101................................................................................................................................................................
Program Ram102................................................................................................................................................................
Bootstrap Rom102................................................................................................................................................................
Data Memory Spaces103................................................................................................................................................................
X Data Memory Space103................................................................................................................................................................
Y Data Memory Space104................................................................................................................................................................
Memory Space Configuration104................................................................................................................................................................
Ram Configuration105................................................................................................................................................................
Dsp56300 Ram Patch Mechanism106................................................................................................................................................................
Sample Code For Dsp56305 Patch Mechanism106................................................................................................................................................................
Memory Configuration107................................................................................................................................................................
Memory Configurations108................................................................................................................................................................
Memory Space Configurations108................................................................................................................................................................
Ram Configurations108................................................................................................................................................................
Memory Maps109................................................................................................................................................................
Figure 3-1 Default Memory Configuration110................................................................................................................................................................
Figure 3-2 Instruction Cache Enabled111................................................................................................................................................................
Figure 3-3 Memory Switch Enabled112................................................................................................................................................................
Figure 3-4 Memory Switch Enabled, Instruction Cache Enabled113................................................................................................................................................................
Figure 3-5 Sixteen-bit Compatibility Mode114................................................................................................................................................................
Figure 3-6 Sixteen-bit Compatibility Mode, Instruction Cache Enabled115................................................................................................................................................................
Figure 3-7 Sixteen-bit Compatibility Mode, Memory Switch Enabled116................................................................................................................................................................
Instruction Cache Enabled117................................................................................................................................................................
Internal And External I/o Memory Map118................................................................................................................................................................
Section 4 Core Configuration119................................................................................................................................................................
Core Configuration119................................................................................................................................................................
Operating Modes121................................................................................................................................................................
Bootstrap Program123................................................................................................................................................................
Mode 0: Expanded Mode124................................................................................................................................................................
Modes 1–3: Bootstrap According To Rtos Mode125................................................................................................................................................................
Modes 4–7: Reserved125................................................................................................................................................................
Mode 8: Expanded Mode126................................................................................................................................................................
Mode 9: Bootstrap From Byte-wide External Memory126................................................................................................................................................................
Mode A: Bootstrap Through Sci126................................................................................................................................................................
Mode C: Bootstrap Through Hi32 In Pci Mode127................................................................................................................................................................
Double-strobe Pin Configuration128................................................................................................................................................................
Single-strobe Pin Configuration129................................................................................................................................................................
Rtos Program129................................................................................................................................................................
Interrupt Sources And Priorities129................................................................................................................................................................
Interrupt Sources130................................................................................................................................................................
Interrupt Priority Levels133................................................................................................................................................................
Figure 4-1 Interrupt Priority Register C (ipr-c) (x:$ffffff)134................................................................................................................................................................
Interrupt Source Priorities Within An Ipl135................................................................................................................................................................
Figure 4-2 Interrupt Priority Register P (ipr-p) (x:$fffffe)135................................................................................................................................................................
Dma Request Sources138................................................................................................................................................................
Operating Mode Register (omr)140................................................................................................................................................................
Address Tracing Enable (ate)—omr Bit 15140................................................................................................................................................................
Pll Control Register141................................................................................................................................................................
Pll Multiplication Factor (mf11:0)—pctl Bits 0–11141................................................................................................................................................................
Crystal Range (xtlr)—pctl Bit 15141................................................................................................................................................................
Figure 4-3 Dsp56305 Operating Mode Register (omr)141................................................................................................................................................................
Figure 4-4 Pll Control Register (pctl)141................................................................................................................................................................
Xtal Disable (xtld)—pctl Bit 16142................................................................................................................................................................
Predivider Factor Bits (pd3:0)—pctl Bits 20–23142................................................................................................................................................................
Device Identification Register142................................................................................................................................................................
Jtag Identification (id) Register143................................................................................................................................................................
Jtag Boundary Scan Register (bsr)143................................................................................................................................................................
Figure 4-6 Jtag Identification Register Configuration (revision 0)143................................................................................................................................................................
Section 5 General Purpose I/o145................................................................................................................................................................
Programming Model147................................................................................................................................................................
Port B Signals And Registers147................................................................................................................................................................
Port C Signals And Registers147................................................................................................................................................................
Port D Signals And Registers148................................................................................................................................................................
Port E Signals And Registers148................................................................................................................................................................
Triple Timer Signals148................................................................................................................................................................
Section 6 Host Interface (hi32)149................................................................................................................................................................
Introduction To The Host Interface (hi32)151................................................................................................................................................................
Hi32 Features152................................................................................................................................................................
Interface - Dsp56300 Core Side152................................................................................................................................................................
Interface - Host Side154................................................................................................................................................................
Hi32 Features In Pci Mode155................................................................................................................................................................
Hi32 Features In Universal Bus Modes156................................................................................................................................................................
Hi32 Resets157................................................................................................................................................................
Hi32 Block Diagram158................................................................................................................................................................
Figure 6-1 Hi32 Block Diagram158................................................................................................................................................................
Dsp Side Programming Model159................................................................................................................................................................
Dsp Control Register (dctr)160................................................................................................................................................................
Host Command Interrupt Enable (hcie) Bit 0161................................................................................................................................................................
Slave Transmit Interrupt Enable (stie) Bit 1161................................................................................................................................................................
Slave Receive Interrupt Enable (srie) Bit 2161................................................................................................................................................................
Host Flags (hf[5:3]) Bits 5-3161................................................................................................................................................................
Host Interrupt A (hint) Bit 6161................................................................................................................................................................
Host Data Strobe Mode (hdsm) Bit 13162................................................................................................................................................................
Host Read/write Polarity (hrwp) Bit 14162................................................................................................................................................................
Host Transfer Acknowledge Polarity (htap) Bit 15163................................................................................................................................................................
Host Dma Request Polarity (hdrp) Bit 16163................................................................................................................................................................
Host Reset Polarity (hrsp) Bit 17163................................................................................................................................................................
Host Interrupt Request Handshake Mode(hirh) Bit 18164................................................................................................................................................................
Host Interrupt Request Drive Control (hird) Bit 19164................................................................................................................................................................
Hi32 Mode (hm2-hm0) Bits 22-20165................................................................................................................................................................
Terminate And Reset (hm[2:0] = 000)165................................................................................................................................................................
Pci Mode (hm = $1)166................................................................................................................................................................
Universal Bus Mode (hm = $2)166................................................................................................................................................................
Enhanced Universal Bus Mode (hm = $3):167................................................................................................................................................................
Gpio Mode (hm = $4):167................................................................................................................................................................
Self Configuration Mode (hm = $5):167................................................................................................................................................................
Dctr Reserved Control Bits 23, 12-7168................................................................................................................................................................
Dsp Pci Control Register (dpcr)169................................................................................................................................................................
Master Transmit Interrupt Enable (mtie) Bit 1170................................................................................................................................................................
Master Receive Interrupt Enable (mrie) Bit 2170................................................................................................................................................................
Master Address Interrupt Enable (maie) Bit 4170................................................................................................................................................................
Parity Error Interrupt Enable (peie) Bit 5170................................................................................................................................................................
Transaction Abort Interrupt Enable (taie) Bit 7170................................................................................................................................................................
Transaction Termination Interrupt Enable (ttie) Bit 9171................................................................................................................................................................
Transfer Complete Interrupt Enable (tcie) Bit 12171................................................................................................................................................................
Clear Transmitter (clrt) Bit 14171................................................................................................................................................................
Master Transaction Termination (mtt) Bit 15172................................................................................................................................................................
System Error Force (serf) Bit 16172................................................................................................................................................................
Master Access Counter Enable (mace) Bit 18173................................................................................................................................................................
Master Wait State Disable (mwsd) Bit 19173................................................................................................................................................................
Receive Buffer Lock Enable (rble) Bit 20174................................................................................................................................................................
Insert Address Enable (iae) Bit 21175................................................................................................................................................................
Dsp Pci Master Control Register(dpmc)176................................................................................................................................................................
Dsp Pci Transaction Address (ar31-ar16) Bits 15-0176................................................................................................................................................................
Dsp Pci Data Burst Length (bl5-bl0) Bits 21-16177................................................................................................................................................................
In A Pci Dsp-to-host Transaction:179................................................................................................................................................................
If Fc = $0 (32-bit Data Mode):179................................................................................................................................................................
If Fc = $1:179................................................................................................................................................................
If Fc = $2:179................................................................................................................................................................
If Fc = $3:179................................................................................................................................................................
In A Pci Host-to-dsp Transaction:179................................................................................................................................................................
Dsp Pci Address Register (dpar)180................................................................................................................................................................
Pci Bus Command (c3-c0) Bits 11-8181................................................................................................................................................................
Pci Byte Enables (be3-be0) Bits 15-12182................................................................................................................................................................
Dsp Status Register (dsr)183................................................................................................................................................................
Host Command Pending (hcp) Bit 0183................................................................................................................................................................
Slave Transmit Data Request (strq) Bit 1183................................................................................................................................................................
Slave Receive Data Request (srrq) Bit 2184................................................................................................................................................................
Host Flags (hf2-hf0) Bits 5-3185................................................................................................................................................................
Hi32 Active (hact) Bit 23185................................................................................................................................................................
Dsr Reserved Status Bits 22-6185................................................................................................................................................................
Dsp Pci Status Register (dpsr)186................................................................................................................................................................
Pci Master Wait State (mws) Bit 0187................................................................................................................................................................
Pci Master Transmit Data Request (mtrq) Bit 1187................................................................................................................................................................
Pci Master Receive Data Request (mrrq) Bit 2188................................................................................................................................................................
Master Address Request (marq) Bit 4188................................................................................................................................................................
Address Parity Error (aper) Bit 5188................................................................................................................................................................
Data Parity Error (dper) Bit 6189................................................................................................................................................................
Master Abort (mab) Bit 7189................................................................................................................................................................
Target Abort (tab) Bit 8189................................................................................................................................................................
Target Disconnect (tdis) Bit 9189................................................................................................................................................................
Target Retry (trty) Bit 10190................................................................................................................................................................
Pci Time Out (to) Bit 11190................................................................................................................................................................
Host Data Transfer Complete (hdtc) Bit 12190................................................................................................................................................................
Remaining Data Count (rdc5-rdc0) Bits 21-16191................................................................................................................................................................
Dpsr Reserved Bits 23-22, 15-12 And 3191................................................................................................................................................................
Host To Dsp Data Path191................................................................................................................................................................
Dsp Receive Data Fifo (drxr)192................................................................................................................................................................
Dsp To Host Data Path192................................................................................................................................................................
Dsp Master Transmit Data Register (dtxm)193................................................................................................................................................................
Dsp Slave Transmit Data Register (dtxs)194................................................................................................................................................................
Dsp Host Port Gpio Data Register (dath)194................................................................................................................................................................
Dsp Host Port Gpio Direction Register (dirh)195................................................................................................................................................................
Host Side Programming Model196................................................................................................................................................................
Figure 6-2 Host Side Registers (pci Memory Address Space)200................................................................................................................................................................
Figure 6-3 Host Side Registers (pci Configuration Address Space)200................................................................................................................................................................
Figure 6-4 Host Side Registers (universal Bus Mode Address Space)201................................................................................................................................................................
Hi32 Control Register (hctr)202................................................................................................................................................................
Transmit Request Enable (treq) Bit 1203................................................................................................................................................................
Receive Request Enable (rreq) Bit 2204................................................................................................................................................................
Host Flags (hf2-hf0) Bits 5 And 3205................................................................................................................................................................
Dma Enable (dmae) Bit 6205................................................................................................................................................................
Slave Fetch Type (sft) Bit 7206................................................................................................................................................................
Host Semaphores (hs2-hs0) Bits 16 And 14212................................................................................................................................................................
Target Wait State Disable (twsd) Bit 19212................................................................................................................................................................
Bits 31-20, 18-17, 13, 10, And 0215................................................................................................................................................................
Hi32 Status Register (hstr)216................................................................................................................................................................
Transmitter Ready (trdy) Bit 0217................................................................................................................................................................
Host Transmit Data Request (htrq) Bit 1217................................................................................................................................................................
Host Receive Data Request (hrrq) Bit 2218................................................................................................................................................................
Host Flags (hf5-hf3) Bits 5, 4 And 3218................................................................................................................................................................
Host Request (hreq) Bit 7219................................................................................................................................................................
Hstr Reserved Status Bits 31-8219................................................................................................................................................................
Host Command Vector Register (hcvr)220................................................................................................................................................................
Host Command (hc) Bit 0221................................................................................................................................................................
Host Vector (hv6-hv0) Bits 7-1222................................................................................................................................................................
Host Non-maskable Interrupt (hnmi) Bit 15222................................................................................................................................................................
Hcvr Reserved Bits 31-16, 14-8222................................................................................................................................................................
Host Slave Receive Data Register (hrxs)223................................................................................................................................................................
Host Master Receive Data Register (hrxm)224................................................................................................................................................................
Host Transmit Data Register (htxr)224................................................................................................................................................................
Device/vendor Id Configuration Register (cdid/cvid)226................................................................................................................................................................
Status/command Configuration Register (cstr/ccmr)226................................................................................................................................................................
Memory Space Enable (mse) Bit 1228................................................................................................................................................................
Bus Master Enable (bm) Bit 2228................................................................................................................................................................
Parity Error Response (perr) Bit 6228................................................................................................................................................................
Wait Cycle Control (wcc) Bit 7228................................................................................................................................................................
System Error Enable (sere) Bit 8229................................................................................................................................................................
Fast Back-to-back Capable (fbbc) Bit 23229................................................................................................................................................................
Data Parity Reported (dpr) Bit 24229................................................................................................................................................................
Devsel Timing (dst1-dst0) Bits 26 And 25229................................................................................................................................................................
Signaled Target Abort (sta) Bit 27229................................................................................................................................................................
Received Target Abort (rta) Bit 28229................................................................................................................................................................
Received Master Abort (rma) Bit 29230................................................................................................................................................................
Signaled System Error (sse) Bit 30230................................................................................................................................................................
Detected Parity Error (dpe) Bit 31230................................................................................................................................................................
Cstr Reserved Bits 23-16230................................................................................................................................................................
Ccmr Reserved Bits 15-10230................................................................................................................................................................
Ccmr Not Implemented Bits 9, 5-3230................................................................................................................................................................
Header Type (ht7-ht0) Bits 23-16232................................................................................................................................................................
Latency Timer (lt7-lt0) Bits 15-8233................................................................................................................................................................
Chty/clat Not Implemented Bits 31-24,7-0233................................................................................................................................................................
Memory Space Indicator (msi) Bit 0234................................................................................................................................................................
Memory Space (ms1-ms0) Bits 2 And 1235................................................................................................................................................................
Pre-fetch (pf) Bit 3235................................................................................................................................................................
Memory Base Address (pm31-pm16) Bits 31-4235................................................................................................................................................................
Bits 23-16235................................................................................................................................................................
Self Configuration Mode237................................................................................................................................................................
Self Configuration Procedure For The Pci Mode238................................................................................................................................................................
Self Configuration Procedure For The Universal Bus Mode238................................................................................................................................................................
Host Port Signals239................................................................................................................................................................
Interrupt Vectors254................................................................................................................................................................
Via Programming254................................................................................................................................................................
Examples Of Host To Hi32 Connections255................................................................................................................................................................
Figure 6-7 Example Of Connection To Dsp56300 Core Port A Bus257................................................................................................................................................................
Essi Enhancements260................................................................................................................................................................
Essi Data And Control Signals262................................................................................................................................................................
Serial Transmit Data Signal (std)262................................................................................................................................................................
Serial Receive Data Signal (srd)263................................................................................................................................................................
Serial Clock (sck)264................................................................................................................................................................
Serial Control Signal (sc0)266................................................................................................................................................................
Serial Control Signal (sc1)268................................................................................................................................................................
Serial Control Signal (sc2)270................................................................................................................................................................
Essi Programming Model271................................................................................................................................................................
Essi Control Register A (cra)273................................................................................................................................................................
Normal Mode (mod = 0)275................................................................................................................................................................
Network Mode (mod = 1; Dc ≠ 00000)275................................................................................................................................................................
On-demand Mode (mod = 1; Dc = 00000)275................................................................................................................................................................
Essi Control Register B (crb)278................................................................................................................................................................
Serial Output Flag 0 (of0) Crb Bit 0278................................................................................................................................................................
Serial Output Flag 1 (of1) Crb Bit 1279................................................................................................................................................................
Serial Control Direction 0 (scd0) Crb Bit 2279................................................................................................................................................................
Serial Control Direction 1 (scd1) Crb Bit 3280................................................................................................................................................................
Serial Control Direction 2 (scd2) Crb Bit 4280................................................................................................................................................................
Clock Source Direction (sckd) Crb Bit 5280................................................................................................................................................................
Shift Direction (shfd) Crb Bit 6280................................................................................................................................................................
Frame Sync Relative Timing (fsr) Crb Bit 9281................................................................................................................................................................
Figure 7-16 Crb Fsl[1:0] Bit Operation283................................................................................................................................................................
Essi Mode Select (mod) Crb Bit 13284................................................................................................................................................................
Figure 7-17 Crb Syn Bit Operation284................................................................................................................................................................
From The Essi286................................................................................................................................................................
Essi Transmit 2 Enable (te2) Crb Bit 14286................................................................................................................................................................
Essi Transmit 1 Enable (te1) Crb Bit 15287................................................................................................................................................................
Essi Transmit 0 Enable (te0) Crb Bit 16288................................................................................................................................................................
Essi Receive Enable (re) Crb Bit 17290................................................................................................................................................................
Essi Transmit Interrupt Enable (tie) Crb Bit 18291................................................................................................................................................................
Essi Receive Interrupt Enable (rie) Crb Bit 19291................................................................................................................................................................
Essi Status Register (ssisr)292................................................................................................................................................................
Serial Input Flag 0 (if0) Ssisr Bit 0292................................................................................................................................................................
Serial Input Flag 1 (if1) Ssisr Bit 1293................................................................................................................................................................
Transmit Frame Sync Flag (tfs) Ssisr Bit 2293................................................................................................................................................................
Receive Frame Sync Flag (rfs) Ssisr Bit 3293................................................................................................................................................................
Transmitter Underrun Error Flag (tue) Ssisr Bit 4294................................................................................................................................................................
Receiver Overrun Error Flag (roe) Ssisr Bit 5294................................................................................................................................................................
Essi Transmit Data Register Empty (tde) Ssisr Bit 6294................................................................................................................................................................
Essi Receive Data Register Full (rdf) Ssisr Bit 7294................................................................................................................................................................
Figure 7-19 Essi Data Path Programming Model (shfd = 0)295................................................................................................................................................................
Figure 7-20 Essi Data Path Programming Model (shfd = 1)296................................................................................................................................................................
Essi Receive Shift Register297................................................................................................................................................................
Essi Receive Data Register (rx)297................................................................................................................................................................
Essi Transmit Shift Registers297................................................................................................................................................................
Essi Transmit Data Registers298................................................................................................................................................................
Essi Time Slot Register (tsr)298................................................................................................................................................................
Transmit Slot Mask Registers (tsma, Tsmb)298................................................................................................................................................................
Receive Slot Mask Registers (rsma, Rsmb)299................................................................................................................................................................
Essi Initialization300................................................................................................................................................................
Essi Exceptions302................................................................................................................................................................
Essi Exception Types302................................................................................................................................................................
Exception Configuration303................................................................................................................................................................
Normal Mode (crb(mod) = 0)305................................................................................................................................................................
Network Mode (crb(mod) = 1; Cra(dc) ≠ 00000)305................................................................................................................................................................
Figure 7-21 Essi Main Modes305................................................................................................................................................................
On-demand Mode (crb(mod) = 1, Dc = 00000)307................................................................................................................................................................
Synchronous/asynchronous Operating Modes307................................................................................................................................................................
Frame Sync Settings308................................................................................................................................................................
Frame Sync Signal Format308................................................................................................................................................................
Frame Sync Length For Multiple Devices308................................................................................................................................................................
Word Length Frame Sync Position308................................................................................................................................................................
Frame Sync Polarity309................................................................................................................................................................
Selecting The Bit Shift Order For The Transmitter309................................................................................................................................................................
Essi Flag Usage310................................................................................................................................................................
Gpio/essi Selection And Gpio Usage310................................................................................................................................................................
Port Control Register (pcr)311................................................................................................................................................................
Figure 7-22 Gpio/essi Port Organization311................................................................................................................................................................
Figure 7-23 Port Control Register (pcr)311................................................................................................................................................................
Port Direction Register (prr)312................................................................................................................................................................
Figure 7-24 Port Direction Register (prr)312................................................................................................................................................................
Port Data Register (pdr)313................................................................................................................................................................
Figure 7-25 Port Data Register (pdr)313................................................................................................................................................................
Section 8 Serial Communication Interface (sci)315................................................................................................................................................................
Sci I/o Signals317................................................................................................................................................................
Receive Data (rxd)318................................................................................................................................................................
Transmit Data (txd)318................................................................................................................................................................
Sci Serial Clock (sclk)318................................................................................................................................................................
Sci Programming Model319................................................................................................................................................................
Figure 8-1 Sci Control Register (scr)320................................................................................................................................................................
Figure 8-2 Sci Status Register (ssr)320................................................................................................................................................................
Figure 8-3 Sci Clock Control Register (sccr)320................................................................................................................................................................
Figure 8-4 Sci Data Word Formats (ssftd=0)321................................................................................................................................................................
Figure 8-5 Sci Data Word Formats (ssftd=1)322................................................................................................................................................................
Sci Control Register (scr)323................................................................................................................................................................
Word Select (wds[0:2]) Scr Bits 0-2323................................................................................................................................................................
Sci Shift Direction (ssftd) Scr Bit 3324................................................................................................................................................................
Send Break (sbk) Scr Bit 4324................................................................................................................................................................
Wakeup Mode Select (wake) Scr Bit 5324................................................................................................................................................................
Receiver Wakeup Enable (rwu) Scr Bit 6325................................................................................................................................................................
Wired-or Mode Select (woms) Scr Bit 7325................................................................................................................................................................
Receiver Enable (re) Scr Bit 8325................................................................................................................................................................
Transmitter Enable (te) Scr Bit 9326................................................................................................................................................................
Idle Line Interrupt Enable (ilie) Scr Bit 10326................................................................................................................................................................
Sci Receive Interrupt Enable (rie) Scr Bit 11327................................................................................................................................................................
Sci Transmit Interrupt Enable (tie) Scr Bit 12327................................................................................................................................................................
Timer Interrupt Enable (tmie) Scr Bit 13327................................................................................................................................................................
Timer Interrupt Rate (stir) Scr Bit 14327................................................................................................................................................................
Sci Clock Polarity (sckp) Scr Bit 15328................................................................................................................................................................
Reie) Scr Bit 16328................................................................................................................................................................
Sci Status Register (ssr)328................................................................................................................................................................
Transmitter Empty (trne) Ssr Bit 0328................................................................................................................................................................
Transmit Data Register Empty (tdre) Ssr Bit 1328................................................................................................................................................................
Receive Data Register Full (rdrf) Ssr Bit 2329................................................................................................................................................................
Idle Line Flag (idle) Ssr Bit 3329................................................................................................................................................................
Overrun Error Flag (or) Ssr Bit 4329................................................................................................................................................................
Parity Error (pe) Ssr Bit 5330................................................................................................................................................................
Framing Error Flag (fe) Ssr Bit 6330................................................................................................................................................................
Received Bit 8 Address (r8) Ssr Bit 7330................................................................................................................................................................
Sci Clock Control Register (sccr)331................................................................................................................................................................
Clock Divider (cd[11:0]) Sccr Bits 11–0332................................................................................................................................................................
Clock Out Divider (cod) Sccr Bit 12332................................................................................................................................................................
Sci Clock Prescaler (scp) Sccr Bit 13332................................................................................................................................................................
Figure 8-6 16 X Serial Clock332................................................................................................................................................................
Receive Clock Mode Source Bit (rcm) Sccr Bit 14333................................................................................................................................................................
Figure 8-7 Sci Baud Rate Generator333................................................................................................................................................................
Transmit Clock Source Bit (tcm) Sccr Bit 15334................................................................................................................................................................
Sci Data Registers334................................................................................................................................................................
Figure 8-8 Sci Programming Model - Data Registers334................................................................................................................................................................
Sci Receive Registers (srx)335................................................................................................................................................................
Sci Transmit Registers335................................................................................................................................................................
Sci After Reset338................................................................................................................................................................
Sci Initialization341................................................................................................................................................................
Sci Initialization Example341................................................................................................................................................................
Preamble, Break, And Data Transmission Priority342................................................................................................................................................................
Sci Exceptions343................................................................................................................................................................
Gpio Signals And Registers343................................................................................................................................................................
Port E Control Register (pcre)343................................................................................................................................................................
Port E Direction Register (prre)344................................................................................................................................................................
Figure 8-9 Port E Control Register (pcre)344................................................................................................................................................................
Figure 8-10 Port E Direction Register (prre)344................................................................................................................................................................
Port E Data Register (pdre)345................................................................................................................................................................
Figure 8-11 Port E Data Register (pdre)345................................................................................................................................................................
Section 9 Timer/event Counter347................................................................................................................................................................
Timer/event Counter347................................................................................................................................................................
Introduction To The Timer/event Counter349................................................................................................................................................................
Timer/event Counter Architecture349................................................................................................................................................................
Timer/event Counter Block Diagram350................................................................................................................................................................
Timer/event Counter Programming Model350................................................................................................................................................................
Figure 9-1 Timer/event Counter Block Diagram350................................................................................................................................................................
Prescaler Counter351................................................................................................................................................................
Timer Prescaler Load Register (tplr)351................................................................................................................................................................
Figure 9-2 Timer/event Counter Programming Model351................................................................................................................................................................
Figure 9-3 Timer Prescaler Load Register (tplr)351................................................................................................................................................................
Prescaler Preload Value Pl[20:0] — Tplr Bits 20-0352................................................................................................................................................................
Prescaler Source Ps[1:0] — Tplr Bits 22-21352................................................................................................................................................................
Reserved Bit — Tplr Bit 23352................................................................................................................................................................
Timer Prescaler Count Register (tpcr)353................................................................................................................................................................
Prescaler Counter Value Pc[20:0] — Tpcr Bits 20-0353................................................................................................................................................................
Reserved Bits — Tpcr Bits 23-21353................................................................................................................................................................
Timer Architecture353................................................................................................................................................................
Figure 9-4 Timer Prescaler Count Register (tpcr)353................................................................................................................................................................
Timer Block Diagram355................................................................................................................................................................
Timer Programming Model355................................................................................................................................................................
Figure 9-5 Timer Block Diagram355................................................................................................................................................................
Timer Control/status Register (tcsr)356................................................................................................................................................................
Figure 9-6 Timer Programming Model356................................................................................................................................................................
Timer Enable (te) — Tcsr Bit 0357................................................................................................................................................................
Toie) — Tcsr Bit 1357................................................................................................................................................................
Tcie) — Tcsr Bit 2357................................................................................................................................................................
Timer Control (tc[3:0]) — Tcsr Bits 4-7357................................................................................................................................................................
Inverter (inv) — Tcsr Bit 8359................................................................................................................................................................
Timer Reload Mode (trm) — Tcsr Bit 9360................................................................................................................................................................
Direction (dir) — Tcsr Bit 11361................................................................................................................................................................
Data Input (di) — Tcsr Bit 12361................................................................................................................................................................
Data Output (do) — Tcsr Bit 13361................................................................................................................................................................
Prescaler Clock Enable (pce) — Tcsr Bit 15362................................................................................................................................................................
Timer Overflow Flag (tof) — Tcsr Bit 20362................................................................................................................................................................
Timer Compare Flag (tcf) — Tcsr Bit 21362................................................................................................................................................................
Reserved Bits — Tcsr Bits 3, 10, 14, 16-19, 22, 23362................................................................................................................................................................
Timer Load Register (tlr)363................................................................................................................................................................
Timer Compare Register (tcpr)363................................................................................................................................................................
Timer Count Register (tcr)363................................................................................................................................................................
Timer Modes Of Operation364................................................................................................................................................................
Timer Modes365................................................................................................................................................................
Timer Gpio (mode 0)365................................................................................................................................................................
Timer Pulse (mode 1)366................................................................................................................................................................
Timer Toggle (mode 2)367................................................................................................................................................................
Timer Event Counter (mode 3)368................................................................................................................................................................
Signal Measurement Modes369................................................................................................................................................................
Measurement Accuracy369................................................................................................................................................................
Measurement Input Width (mode 4)369................................................................................................................................................................
Measurement Input Period (mode 5)370................................................................................................................................................................
Measurement Capture (mode 6)371................................................................................................................................................................
Pulse Width Modulation (pwm, Mode 7)372................................................................................................................................................................
Watchdog Modes373................................................................................................................................................................
Watchdog Pulse (mode 9)373................................................................................................................................................................
Watchdog Toggle (mode 10)374................................................................................................................................................................
Reserved Modes375................................................................................................................................................................
Special Cases375................................................................................................................................................................
Timer Behavior During Wait375................................................................................................................................................................
Timer Behavior During Stop375................................................................................................................................................................
Dma Trigger375................................................................................................................................................................
Section 10 On-chip Emulation Module377................................................................................................................................................................
On-chip Emulation Module377................................................................................................................................................................
Once Module Signals379................................................................................................................................................................
Figure 10-1 Once Module Block Diagram379................................................................................................................................................................
Debug Event (de)380................................................................................................................................................................
Figure 10-2 Once Module Multiprocessor Configuration380................................................................................................................................................................
Once Controller381................................................................................................................................................................
Once Command Register (ocr)381................................................................................................................................................................
Figure 10-3 Once Controller Block Diagram381................................................................................................................................................................
Figure 10-4 Once Command Register381................................................................................................................................................................
Register Select (rs4–rs0) Bits 0–4382................................................................................................................................................................
Exit Command (ex) Bit 5382................................................................................................................................................................
Go Command (go) Bit 6382................................................................................................................................................................
Read/write Command (r/w) Bit 7382................................................................................................................................................................
Once Decoder (odec)384................................................................................................................................................................
Once Status And Control Register (oscr)384................................................................................................................................................................
Trace Mode Enable (tme) Bit 0384................................................................................................................................................................
Interrupt Mode Enable (ime) Bit 1384................................................................................................................................................................
Figure 10-5 Once Status And Control Register (oscr)384................................................................................................................................................................
Software Debug Occurrence (swo) Bit 2385................................................................................................................................................................
Memory Breakpoint Occurrence (mbo) Bit 3385................................................................................................................................................................
Trace Occurrence (to) Bit 4385................................................................................................................................................................
Reserved Ocsr Bit 5385................................................................................................................................................................
Core Status (os0, Os1) Bits 6-7385................................................................................................................................................................
Reserved Bits 8-23386................................................................................................................................................................
Once Memory Breakpoint Logic386................................................................................................................................................................
Figure 10-6 Once Memory Breakpoint Logic 0386................................................................................................................................................................
Once Memory Address Latch (omal)387................................................................................................................................................................
Once Memory Limit Register 0 (omlr0)387................................................................................................................................................................
Once Memory Address Comparator 0 (omac0)387................................................................................................................................................................
Once Memory Limit Register 1 (omlr1)387................................................................................................................................................................
Once Memory Address Comparator 1 (omac1)387................................................................................................................................................................
Once Breakpoint Control Register (obcr)388................................................................................................................................................................
Bits 0–1388................................................................................................................................................................
Bits 2–3388................................................................................................................................................................
Figure 10-7 Once Breakpoint Control Register (obcr)388................................................................................................................................................................
Bits 4–5389................................................................................................................................................................
Bits 6–7389................................................................................................................................................................
Bits 8–9390................................................................................................................................................................
Bits10–11390................................................................................................................................................................
Once Memory Breakpoint Counter (ombc)390................................................................................................................................................................
Reserved Bits 12-15391................................................................................................................................................................
Once Trace Logic391................................................................................................................................................................
Figure 10-8 Once Trace Logic Block Diagram391................................................................................................................................................................
Methods Of Entering The Debug Mode392................................................................................................................................................................
External Debug Request During Reset Assertion392................................................................................................................................................................
External Debug Request During Normal Activity392................................................................................................................................................................
Executing The Jtag Debug_request Instruction393................................................................................................................................................................
External Debug Request During Stop Mode393................................................................................................................................................................
External Debug Request During Wait Mode393................................................................................................................................................................
Software Request During Normal Activity394................................................................................................................................................................
Enabling Trace Mode394................................................................................................................................................................
Enabling Memory Breakpoints394................................................................................................................................................................
Pipeline Information And Ogdbr394................................................................................................................................................................
Once Pdb Register (opdbr)395................................................................................................................................................................
Once Pil Register (opilr)395................................................................................................................................................................
Figure 10-9 Once Pipeline Information And Gdb Registers395................................................................................................................................................................
Once Gdb Register (ogdbr)396................................................................................................................................................................
Trace Buffer396................................................................................................................................................................
Once Pab Register For Fetch (opabfr)396................................................................................................................................................................
Pab Register For Decode (opabdr)396................................................................................................................................................................
Once Pab Register For Execute (opabex)397................................................................................................................................................................
Figure 10-10 Once Trace Buffer398................................................................................................................................................................
Once Commands And Serial Protocol399................................................................................................................................................................
Target Site Debug System Requirements399................................................................................................................................................................
Examples Of Using The Once400................................................................................................................................................................
Whether The Chip Has Entered The Debug Mode400................................................................................................................................................................
Polling The Jtag Instruction Shift Register400................................................................................................................................................................
Saving Pipeline Information401................................................................................................................................................................
Reading The Trace Buffer401................................................................................................................................................................
Displaying A Specified Register402................................................................................................................................................................
Displaying X Memory Area Starting At Address $xxxx403................................................................................................................................................................
Going From Debug To Normal Mode In A Current Program404................................................................................................................................................................
Going From Debug To Normal Mode In A New Program404................................................................................................................................................................
Examples Of Jtag And Once Interaction405................................................................................................................................................................
Section 11 Jtag Port411................................................................................................................................................................
Jtag Port411................................................................................................................................................................
Figure 11-1 Tap Block Diagram414................................................................................................................................................................
Jtag Signals415................................................................................................................................................................
Test Clock (tck)415................................................................................................................................................................
Test Mode Select (tms)415................................................................................................................................................................
Test Data Input (tdi)415................................................................................................................................................................
Test Data Output (tdo)415................................................................................................................................................................
Test Reset (trst)415................................................................................................................................................................
Tap Controller416................................................................................................................................................................
Figure 11-2 Tap Controller State Machine416................................................................................................................................................................
Boundary Scan Register417................................................................................................................................................................
Instruction Register417................................................................................................................................................................
Figure 11-3 Jtag Instruction Register417................................................................................................................................................................
Extest (b[3:0] = 0000)419................................................................................................................................................................
Sample/preload (b[3:0] = 0001)419................................................................................................................................................................
Idcode (b[3:0] = 0010)419................................................................................................................................................................
Clamp (b[3:0] = 0011)420................................................................................................................................................................
Figure 11-4 Jtag Id Register420................................................................................................................................................................
Hi-z (b[3:0] = 0100)421................................................................................................................................................................
Enable_once(b[3:0] = 0110)421................................................................................................................................................................
Debug_request(b[3:0] = 0111)421................................................................................................................................................................
Bypass (b[3:0] = 1111)422................................................................................................................................................................
Dsp56300 Restrictions422................................................................................................................................................................
Figure 11-5 Bypass Register422................................................................................................................................................................
Dsp56305 Boundary Scan Register423................................................................................................................................................................
Section 12 Filter Co-processor431................................................................................................................................................................
Fcop Support For Gsm433................................................................................................................................................................
Features434................................................................................................................................................................
Block Description434................................................................................................................................................................
Peripheral Module Bus (pmb) Interface435................................................................................................................................................................
Figure 12-1 Filter Co-processor Block Diagram435................................................................................................................................................................
Fcop Memory Banks436................................................................................................................................................................
Multiplier And Accumulator (fmac)436................................................................................................................................................................
Fcop Registers437................................................................................................................................................................
Fcop Data Input Register (fdir)438................................................................................................................................................................
Fcop Data Output Register (fdor)438................................................................................................................................................................
Fcop Coefficients Input Register (fcir)439................................................................................................................................................................
Fcop Filter Count Register (fcnt)439................................................................................................................................................................
Fcop Control/status Register (fcsr)439................................................................................................................................................................
Fcop Enable (fen)—fcsr Bit 0440................................................................................................................................................................
Fcop Operation Mode (fom[1:0])—fcsr Bits 4–5440................................................................................................................................................................
Figure 12-2 Fcop Control/status Register (fcsr)440................................................................................................................................................................
Fcop Decimation (fdcm)—fcsr Bit 8441................................................................................................................................................................
Fcop Data Saturation (fsat)—fcsr Bit 12442................................................................................................................................................................
Fcop Reserved Unused Bits—fcsr Bits 1, 3, 9, 13443................................................................................................................................................................
Fcop Reserved Used Bits—fcsr Bits 2, 6, 7443................................................................................................................................................................
Interrupts And Dma444................................................................................................................................................................
Operation Modes444................................................................................................................................................................
Terminology Used In This Section445................................................................................................................................................................
Input Dma Activation445................................................................................................................................................................
Output Dma Activation446................................................................................................................................................................
Decimation By 2446................................................................................................................................................................
Fcop Mode 0: Real Fir Filter447................................................................................................................................................................
Mode 0 (real Fir Filter), No Decimation447................................................................................................................................................................
Without Decimation448................................................................................................................................................................
Mode 0 (real Fir Filter), Decimation By 2449................................................................................................................................................................
With Decimation By 2450................................................................................................................................................................
Real Outputs Only), Decimation By 2451................................................................................................................................................................
Fcop Mode 1: Full Complex Fir Filter453................................................................................................................................................................
Mode 1(full Complex Fir Filter), No Decimation453................................................................................................................................................................
No Decimation455................................................................................................................................................................
Mode 1 (full Complex Fir Filter), Decimation By 2457................................................................................................................................................................
With Decimation458................................................................................................................................................................
Fcop Mode 2: Full Complex Fir Filter459................................................................................................................................................................
Mode 2 (complex Fir Filter Generating Pure Real And Pure Imaginary Outputs Alternately), Decimation By 2461................................................................................................................................................................
Fcop Mode 3: Optimized Complex Correlation Function464................................................................................................................................................................
Performance Analysis470................................................................................................................................................................
Section 13 Viterbi Co-processor471................................................................................................................................................................
Vcop Support For Gsm473................................................................................................................................................................
Figure 13-1 Block Diagram Of A Typical Data Communication System473................................................................................................................................................................
Mlse Equalizer474................................................................................................................................................................
Figure 13-2 Ungerboeck Form Of Mlse Channel Equalizer474................................................................................................................................................................
Figure 13-3 Vcop Block Diagram476................................................................................................................................................................
Flow Control477................................................................................................................................................................
Branch Metric477................................................................................................................................................................
Add-compare-select (acs)478................................................................................................................................................................
Window Error Detection (wed)478................................................................................................................................................................
Figure 13-4 Window Error Detection Function478................................................................................................................................................................
Trellis479................................................................................................................................................................
Data Control479................................................................................................................................................................
Receive Quality Error479................................................................................................................................................................
Figure 13-5 Bit Error Count Function479................................................................................................................................................................
Equalization Mode480................................................................................................................................................................
Initialization481................................................................................................................................................................
Normal Operation481................................................................................................................................................................
Flush Operation481................................................................................................................................................................
Figure 13-6 Viterbi Co-processor In Equalization Mode481................................................................................................................................................................
Encoder Mode482................................................................................................................................................................
Decoder Mode482................................................................................................................................................................
Figure 13-7 Viterbi Co-processor In Encoder Mode482................................................................................................................................................................
Figure 13-8 Viterbi Co-processor In Decoder Mode483................................................................................................................................................................
Memory Access Mode484................................................................................................................................................................
Flush Mode484................................................................................................................................................................
Vcop Individual Reset State485................................................................................................................................................................
Idle State485................................................................................................................................................................
Viterbi Data Register/fifo (vdr)487................................................................................................................................................................
Viterbi Data Out Register (vdor)487................................................................................................................................................................
Viterbi Control Register A (vcra)488................................................................................................................................................................
Module Enable (me)—vcra Bit 0488................................................................................................................................................................
Memory Access Enable (maen)—vcra Bit 1488................................................................................................................................................................
Figure 13-9 Viterbi Control Register A (vcra)488................................................................................................................................................................
Decoding Enable (decen)—vcra Bit 2489................................................................................................................................................................
Encoding Enable (encen)—vcra Bit 3489................................................................................................................................................................
Equalization Enable (eqen)—vcra Bit 4489................................................................................................................................................................
Flush Enable (flen)—vcra Bit 5489................................................................................................................................................................
Code Rate (rate[1:0])—vcra Bits 8–9490................................................................................................................................................................
Constraint Length (cnst[1:0])—vcra Bit 12–13490................................................................................................................................................................
Vcra Reserved—vcra Bits 6–7, 10–11, 14–15490................................................................................................................................................................
Viterbi Control Register B (vcrb)491................................................................................................................................................................
Initial State Enable (ise)—vcrb Bit 0491................................................................................................................................................................
Flush Control (flc)—vcrb Bit 1491................................................................................................................................................................
Continuous Mode Enable (cme)—vcrb Bit 3491................................................................................................................................................................
Figure 13-10 Viterbi Control Register B (vcrb)491................................................................................................................................................................
Data Mode (hd[0])—vcrb Bits 4–5492................................................................................................................................................................
Window Error Detection Enable (wede)—vcrb Bit 6492................................................................................................................................................................
Data-in Interrupt Enable (diie)—vcrb Bit 8492................................................................................................................................................................
Buffer Full Interrupt Enable (bfie)—vcrb Bit 10492................................................................................................................................................................
Data Out Interrupt Enable (doie)—vcrb Bit 11492................................................................................................................................................................
Reserved Bits—vcrb Bits 2, 5, 9, 14–15492................................................................................................................................................................
Internal Reserved Bits—vcrb Bits 4, 7493................................................................................................................................................................
Viterbi Status Register (vstr)493................................................................................................................................................................
Initialize Flag (init)—vstr Bit 0493................................................................................................................................................................
Flush Flag (flsh)—vstr Bit 1493................................................................................................................................................................
Operation Complete (opc)—vstr Bit 4493................................................................................................................................................................
Figure 13-11 Viterbi Status Register (vstr)493................................................................................................................................................................
Processing Done (done)—vstr Bit 5494................................................................................................................................................................
Data Ready (drdy)—vstr Bit 6494................................................................................................................................................................
End Stage (estg)—vstr Bit 7494................................................................................................................................................................
Data Request (dreq)—vstr Bit 8494................................................................................................................................................................
Data Output Buffer Full (dobf)—vstr Bit 9494................................................................................................................................................................
Reserved Bits—vstr Bits 2, 3, 10–15494................................................................................................................................................................
Viterbi Data Counter (vcnt)495................................................................................................................................................................
Viterbi Tap A Register (vtpa)495................................................................................................................................................................
Tap Vector A (tapa{4:0])—vtpa Bits 4–0495................................................................................................................................................................
Tap Vector B (tapb[4:0])—vtpa Bits 9–5495................................................................................................................................................................
Tap Vector C (tapc[4:0])—vtpa Bits 14–10495................................................................................................................................................................
Reserved Bit—vtpa Bit 15495................................................................................................................................................................
Figure 13-12 Viterbi Tap A Register (vtpa)495................................................................................................................................................................
Viterbi Tap Register B (vtpb)496................................................................................................................................................................
Tap Vector D (tapd{4:0])—vtpb Bits 4–0496................................................................................................................................................................
Tap Vector E (tape[4:0])—vtpb Bits 9–5496................................................................................................................................................................
Tap Vector F (tapf[4:0])—vtpb Bits 14–10496................................................................................................................................................................
Reserved Bit—vtpb Bit 15496................................................................................................................................................................
Figure 13-13 Viterbi Tap Register B (vtpb)496................................................................................................................................................................
Viterbi Trellis Setup Register (vtsr)497................................................................................................................................................................
Initial State (is[5:0])—vtsr Bits 5–0497................................................................................................................................................................
End State (es[5:0])—vtsr Bits 13–8497................................................................................................................................................................
Reserved Bits—vtsr Bits 6, 7, 14, 15497................................................................................................................................................................
Viterbi Bit Error Rate Register/counter (vber)497................................................................................................................................................................
Figure 13-14 Viterbi Trellis Setup Register (vtsr)497................................................................................................................................................................
Viterbi Wed Setup Register (vwes)498................................................................................................................................................................
Figure 13-15 Viterbi Wed Setup Register (vwes)498................................................................................................................................................................
Vwes Bits 7–0499................................................................................................................................................................
Window Length (wlen[7:0])—vwes Bits 15–8499................................................................................................................................................................
Viterbi Wed Data Register (vwed)499................................................................................................................................................................
Viterbi Memory Access Register (vmem)499................................................................................................................................................................
Chip Description500................................................................................................................................................................
Memory Description500................................................................................................................................................................
Interrupt And Dma Sources501................................................................................................................................................................
I/o Register And Related Interrupts For Different Modes501................................................................................................................................................................
Soft Decision Format502................................................................................................................................................................
Viterbi Butterfly Implementation503................................................................................................................................................................
Figure 13-16 Viterbi Butterfly Structure503................................................................................................................................................................
Programming Examples507................................................................................................................................................................
Channel Encode507................................................................................................................................................................
Channel Decode510................................................................................................................................................................
Including Read/write Memory Access515................................................................................................................................................................
References521................................................................................................................................................................
Section 14 Cyclic Code Co-processor523................................................................................................................................................................
Key Features525................................................................................................................................................................
Ccop Block Diagram526................................................................................................................................................................
Cipher Mode Register Configuration526................................................................................................................................................................
Figure 14-1 Ccop Block Diagram526................................................................................................................................................................
Parity Coding Modes Register Configuration527................................................................................................................................................................
Figure 14-2 Cfsr Configuration In The Cipher Modes527................................................................................................................................................................
Ccop Programming Model528................................................................................................................................................................
Figure 14-3 Cfsr Configuration In The Parity Coding Modes528................................................................................................................................................................
Ccop Data Fifo Register (cdfr)530................................................................................................................................................................
Ccop Count Register (ccnt)531................................................................................................................................................................
Input Counter (ic[7:0])—ccnt Bits 7–0531................................................................................................................................................................
Run Counter (rc[7:0])—ccnt Bits 15–8531................................................................................................................................................................
Figure 14-4 Ccop Count Register (ccnt)531................................................................................................................................................................
Output Counter (oc[6:0])—ccnt Bits 22–16532................................................................................................................................................................
Continuous Mode (cm)—ccnt Bit 23532................................................................................................................................................................
Step Function Registers532................................................................................................................................................................
Step Function Select Register (csfs)532................................................................................................................................................................
Select Bit A (sba[4:0])—csfs Bits 4–0533................................................................................................................................................................
Select Register A (sra[1:0])—csfs Bits 6–5533................................................................................................................................................................
Select Bit B (sbb[4:0])—csfs Bits 12–8533................................................................................................................................................................
Select Register B (srb[1:0])—csfs Bits 14–13533................................................................................................................................................................
Figure 14-5 Step Function Select Register (csfs)533................................................................................................................................................................
Select Bit C (sbc[4:0])—csfs Bits 20–16534................................................................................................................................................................
Select Register C (src[1:0])—csfs Bits 22–21534................................................................................................................................................................
Reserved Bits—csfs Bits 7, 15, 23534................................................................................................................................................................
Step Function Table A (csfta)534................................................................................................................................................................
Step Function Table B (csftb)534................................................................................................................................................................
Figure 14-6 Step Function Table A Register (csfta)534................................................................................................................................................................
Input Enable Bits (ine[3:0])—csftb Bits 19–16535................................................................................................................................................................
Figure 14-7 Step Function Table B Register (csftb)535................................................................................................................................................................
Output Enable Bits (oute[3:0])—csftb Bits 23–20536................................................................................................................................................................
Ccop Control Status Register (ccsr)536................................................................................................................................................................
Enable Bit (cen)—ccsr Bit 0537................................................................................................................................................................
Processing Enable Bit (pren)—ccsr Bit 1537................................................................................................................................................................
Operating Mode Bits (opm[1:0])—ccsr Bits 5–4537................................................................................................................................................................
Figure 14-8 Ccop Control Status Register (ccsr)537................................................................................................................................................................
Left-right Connection Bit (lrc)—ccsr Bit 8538................................................................................................................................................................
Halt On Zero Detect Bit (hozd)—ccsr Bit 9538................................................................................................................................................................
Force Shift Bit (fosh)—ccsr Bit 10539................................................................................................................................................................
Data In Interrupt Enable Bit (diie)—ccsr Bit 12539................................................................................................................................................................
Data Out Interrupt Enable Bit (doie)—ccsr Bit 13539................................................................................................................................................................
Input Buffer Empty Bit (inbe)—ccsr Bit 19540................................................................................................................................................................
Input Fifo Empty Bit (infe)—ccsr Bit 20540................................................................................................................................................................
Output Fifo Not Empty Bit (ofne)—ccsr Bit 21540................................................................................................................................................................
Cipher Done Bit (cidn)—ccsr Bit 22540................................................................................................................................................................
Parity Coding Done Bit (pcdn)—ccsr Bit 23541................................................................................................................................................................
Cyclic Code Processing Registers541................................................................................................................................................................
Ccop Linear Feedback Shift Register (cfsrz)542................................................................................................................................................................
Ccop Feedback Tap Register (cfbtz)542................................................................................................................................................................
Ccop Feedforward Tap Register (cfftz)542................................................................................................................................................................
Ccop Bit Select Register (cbsrz)542................................................................................................................................................................
Ccop Mask Register (cmskz)542................................................................................................................................................................
Cipher Modes543................................................................................................................................................................
Normal Cipher Mode543................................................................................................................................................................
Step-by-step Cipher Mode543................................................................................................................................................................
Parity Coding Modes544................................................................................................................................................................
Parity Coding Mode Using One Cfsr544................................................................................................................................................................
Using Two Concatenated Cfsrs544................................................................................................................................................................
Programming Considerations545................................................................................................................................................................
Input Phase545................................................................................................................................................................
Run Phase545................................................................................................................................................................
Output Phase546................................................................................................................................................................
Cipher Mode Processing546................................................................................................................................................................
Cipher Mode Initialization547................................................................................................................................................................
Cipher Mode Output547................................................................................................................................................................
Parity Coding Processing548................................................................................................................................................................
Parity Coding Mode Initialization549................................................................................................................................................................
Parity Coding Mode Output549................................................................................................................................................................
Configuration Examples549................................................................................................................................................................
Programming A General Circuit In Parity Coding Mode549................................................................................................................................................................
Gsm Fire Encode551................................................................................................................................................................
Gsm Fire Decode552................................................................................................................................................................
Appendix A Bootstrap Code555................................................................................................................................................................
A.1 Bootstrap Code For The Dsp56305556................................................................................................................................................................
Appendix B Equates569................................................................................................................................................................
B.1 Internal I/o Equates571................................................................................................................................................................
B.2 Interrupt Equates586................................................................................................................................................................
Appendix C Jtag Bsdl589................................................................................................................................................................
C.1 Jtag Bsdl File591................................................................................................................................................................
Appendix D Programming Reference601................................................................................................................................................................
D.1 Introduction603................................................................................................................................................................
D.1.1 Peripheral Addresses603................................................................................................................................................................
D.1.2 Interrupt Addresses603................................................................................................................................................................
D.1.3 Interrupt Priorities603................................................................................................................................................................
D.1.4 Dma Requests603................................................................................................................................................................
D.1.5 Programming Sheets603................................................................................................................................................................
D.1.6 Hi32 Registers — Quick Reference Tables603................................................................................................................................................................
D.2 Internal I/o Memory Map604................................................................................................................................................................
D.3 Interrupt Addresses And Sources611................................................................................................................................................................
D.4 Interrupt Priorities613................................................................................................................................................................
D.5 Dma Request Sources615................................................................................................................................................................
D.6 Programming Reference Sheets616................................................................................................................................................................
Programming Reference624................................................................................................................................................................
D.7 Quick Reference Tables642................................................................................................................................................................

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