Motorola DSP56305 Manuals

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Motorola DSP56305 User Manual

Motorola DSP56305 User Manual (664 pages)

24-Bit Digital Signal Processor

Brand: Motorola | Category: Signal Processors | Size: 5.47 MB

Table of Contents

Table of Contents

3
List of Tables

35
- Section 1 Dsp56305 Overview
  41
Section 4 Core Configuration

120
Section 10 On-Chip Emulation Module

378
- Figure 10-1 Once Module Block Diagram
  379
- Introduction
  379
- Once Module Signals
  379
- Debug Event (De)
  380
- Figure 10-2 Once Module Multiprocessor Configuration
  380
- Figure 10-3 Once Controller Block Diagram
  381
- Figure 10-4 Once Command Register
  381
- Once Controller
  381
- Exit Command (EX) Bit 5
  382
- GO Command (GO) Bit 6
  382
- Read/Write Command (R/W) Bit 7
  382
- Register Select (RS4–RS0) Bits 0–4
  382
- Table 10-1 EX Bit Definition
  382
- Table 10-2 GO Bit Definition
  382
- Table 10-3 R/W Bit Definition
  382
- Table 10-4 Once Register Select Encoding
  383
- Once Decoder (ODEC)
  384
- Once Memory Address Comparator 0 (OMAC0)
  387
- Once Memory Address Comparator 1 (OMAC1)
  387
  - Once Breakpoint Control Register (OBCR)
    388
- Once Memory Address Latch (OMAL)
  387
- Once Memory Limit Register 0 (OMLR0)
  387
- Once Memory Limit Register 1 (OMLR1)
  387
- Figure 10-7 Once Breakpoint Control Register (OBCR)
  388
  - Bits 0–1
    388
  - Bits 2–3
    388
  - Table 10-6 Memory Breakpoint 0 and 1 Select Table
    388
  - Table 10-7 Breakpoint 0 Read/Write Select Table
    389
  - Table 10-8 Breakpoint 0 Condition Select Table
    389
  - Table 10-9 Breakpoint 1 Read/Write Select Table
    389
  - Bits 4–5
    389
  - Bits 6–7
    389
  - Table 10-10 Breakpoint 1 Condition Select Table
    390
  - Table 10-11 Breakpoint 0 and 1 Event Select Table
    390
  - Bits 8–9
    390
  - Bits10–11
    390
  - Once Memory Breakpoint Counter (OMBC)
    390
  - Reserved Bits 12-15
    391
  - Once Trace Logic
    391
  - Figure 10-8 Once Trace Logic Block Diagram
    391
  - Methods of Entering the Debug Mode
    392
- External Debug Request During Normal Activity
  392
- External Debug Request During RESET Assertion
  392
- Executing the JTAG DEBUG_REQUEST Instruction
  393
  - External Debug Request During Stop Mode
    393
  - External Debug Request During Wait Mode
    393
  - Software Request During Normal Activity
    394
  - Enabling Trace Mode
    394
  - Enabling Memory Breakpoints
    394
  - Pipeline Information and Ogdbr
    394
  - Once PDB Register (OPDBR)
    395
  - Once PIL Register (OPILR)
    395
  - Figure 10-9 Once Pipeline Information and GDB Registers
    395
  - Once GDB Register (OGDBR)
    396
  - Trace Buffer
    396
  - Once PAB Register for Fetch (OPABFR)
    396
  - PAB Register for Decode (OPABDR)
    396
  - Once PAB Register for Execute (OPABEX)
    397
  - Trace Buffer
    397
  - Figure 10-10 Once Trace Buffer
    398
  - Once Commands and Serial Protocol
    399
  - Target Site Debug System Requirements
    399
  - Examples of Using the Once
    400
- Polling the JTAG Instruction Shift Register
  400
- Whether the Chip Has Entered the Debug Mode
  400
- Reading the Trace Buffer
  401
- Saving Pipeline Information
  401
- Displaying a Specified Register
  402
- Displaying X Memory Area Starting at Address $XXXX
  403
- Going from Debug to Normal Mode in a Current Program
  404
- Going from Debug to Normal Mode in a New Program
  404
  - Examples of Jtag and Once Interaction
    405
  - Table 10-14 TMS Sequencing for Reading Pipeline Registers
    407
    
    Section 11 Jtag Port
    411
    
    Introduction
    413
  - Figure 11-1 TAP Block Diagram
    414
  - Jtag Signals
    415
  - Test Clock (TCK)
    415
  - Test Mode Select (TMS)
    415
  - Test Data Input (TDI)
    415
  - Test Data Output (TDO)
    415
  - Test Reset (TRST)
    415
  - Tap Controller
    416
  - Figure 11-2 TAP Controller State Machine
    416
- Boundary Scan Register
  417
- Figure 11-3 JTAG Instruction Register
  417
- Table 11-1 JTAG Instructions
  418
  - Extest (B[3:0] = 0000)
    419
  - Sample/Preload (B[3:0] = 0001)
    419
  - Idcode (B[3:0] = 0010)
    419
  - Clamp (B[3:0] = 0011)
    420
  - Figure 11-4 JTAG ID Register
    420
  - Hi-Z (B[3:0] = 0100)
    421
  - Enable_Once(B[3:0] = 0110)
    421
  - Debug_Request(B[3:0] = 0111)
    421
  - Bypass (B[3:0] = 1111)
    422
  - Dsp56300 Restrictions
    422
  - Figure 11-5 Bypass Register
    422
  - Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions
    423
  - Section 12 Filter Co-Processor
    431
- FCOP Support for GSM
  433
- Introduction
  433
- Block Description
  434
  - Peripheral Module Bus (PMB) Interface
    435
  - Figure 12-1 Filter Co-Processor Block Diagram
    435
- Features
  434
- FCOP Memory Banks
  436
- Multiplier and Accumulator (FMAC)
  436
- Programming Model
  436
- Table 12-1 FCOP Programming Model
  437
- Table 12-2 3 Types of 16-Bit FCOP Registers
  437
- FCOP Data Input Register (FDIR)
  438
- FCOP Data Output Register (FDOR)
  438
- Table 12-3 FCOP Register Read/Write Handling
  438
- FCOP Coefficients Input Register (FCIR)
  439
- FCOP Filter Count Register (FCNT)
  439
  - FCOP Control/Status Register (FCSR)
    439
  - FCOP Enable (FEN)—FCSR Bit 0
    440
- Figure 12-2 FCOP Control/Status Register (FCSR)
  440
  - FCOP Operation Mode (FOM[1:0])—FCSR Bits 4–5
    440
- Table 12-4 FCOP Operation Modes
  440
- Table 12-5 Relationship of FDIIE and FDIBE
  441
  - FCOP Decimation (FDCM)—FCSR Bit 8
    441
- Table 12-6 Relationship of FDOIE and FDOBF
  442
- Operation Modes
  444
- Table 12-7 FCOP Interrupt Vectors and DMA
  444
  - Interrupts and DMA
    444
- Pure Imaginary Outputs Alternately Without Decimation
  460
  - Mode 2 (Complex FIR Filter Generating Pure Real and Pure Imaginary Outputs Alternately), Decimation by 2
    461
- Pure Imaginary Outputs Alternately with Decimation by 2
  463
  - FCOP Mode 3: Optimized Complex Correlation Function
    464
    
    No Decimation
    464
    
    Table 12-8 Non-Oversampled Data Sequence
    465
    
    Figure 12-11 Input and Output Stream for Complex Correlation of Non-Oversampled Data Without Decimation
    466
    
    No Decimation
    467
    
    Table 12-9 2 ¥ Oversampled Data Sequence
    467
    
    Figure 12-12 Input and Output Stream for Complex Correlation of 2× Oversampled Data Without Decimation
    469
    
    Performance Analysis
    470
    
    Table 12-10 FCOP Cycle Count in GSM Base Station
    470
    
    Section 13 Viterbi Co-Processor
    471
  - VCOP Support for GSM
    473
  - Introduction
    473
  - Figure 13-1 Block Diagram of a Typical Data Communication System
    473
  - MLSE Equalizer
    474
  - Figure 13-2 Ungerboeck Form of MLSE Channel Equalizer
    474
    
    Features
    475
    
    Block Description
    476
  - Figure 13-3 VCOP Block Diagram
    476
  - Flow Control
    477
  - Peripheral Module Bus (PMB) Interface
    477
  - Branch Metric
    477
  - Add-Compare-Select (ACS)
    478
  - Window Error Detection (WED)
    478
  - Figure 13-4 Window Error Detection Function
    478
  - Trellis
    479
  - Data Control
    479
  - Receive Quality Error
    479
  - Figure 13-5 Bit Error Count Function
    479
  - Equalization Mode
    480
  - Operating Modes
    480
    
    Figure 13-6 Viterbi Co-Processor in Equalization Mode
    481
    
    Flush Operation
    481
    
    Initialization
    481
    
    Normal Operation
    481
    
    Initialization
    482
  - Decoder Mode
    482
  - Figure 13-7 Viterbi Co-Processor in Encoder Mode
    482
    
    Figure 13-8 Viterbi Co-Processor in Decoder Mode
    483
    
    Initialization
    483
    
    Normal Operation
    483
    
    Flush Operation
    484
  - Memory Access Mode
    484
  - Flush Mode
    484
  - VCOP Individual Reset State
    485
  - Idle State
    485
  - Table 13-1 VCOP Programming Model
    486
  - Viterbi Data Register/Fifo (VDR)
    487
  - Viterbi Data out Register (VDOR)
    487
    
    Memory Access Enable (MAEN)—VCRA Bit 1
    488
    
    Module Enable (ME)—VCRA Bit 0
    488
    
    Viterbi Control Register a (VCRA)
    488
  - Figure 13-9 Viterbi Control Register a (VCRA)
    488
    
    Decoding Enable (DECEN)—VCRA Bit 2
    489
    
    Encoding Enable (ENCEN)—VCRA Bit 3
    489
    
    Equalization Enable (EQEN)—VCRA Bit 4
    489
    
    Flush Enable (FLEN)—VCRA Bit 5
    489
  - Table 13-2 Code Rate Definition
    490
  - Table 13-3 Trellis States
    490
    
    Code Rate (RATE[1:0])—VCRA Bits 8–9
    490
    
    Constraint Length (CNST[1:0])—VCRA Bit 12–13
    490
    
    VCRA Reserved—Vcra Bits 6–7, 10–11, 14–15
    490
    
    Viterbi Control Register B (VCRB)
    491
  - Figure 13-10 Viterbi Control Register B (VCRB)
    491
    
    Continuous Mode Enable (CME)—VCRB Bit 3
    491
    
    Flush Control (FLC)—VCRB Bit 1
    491
    
    Initial State Enable (ISE)—VCRB Bit 0
    491
  - Table 13-4 Flush Modes
    491
  - Table 13-5 Data Modes
    492
    
    Buffer Full Interrupt Enable (BFIE)—VCRB Bit 10
    492
    
    Data Mode (HD[0])—VCRB Bits 4–5
    492
    
    Data out Interrupt Enable (DOIE)—VCRB Bit 11
    492
    
    Data-In Interrupt Enable (DIIE)—VCRB Bit 8
    492
    
    Reserved Bits—Vcrb Bits 2, 5, 9, 14–15
    492
    
    Window Error Detection Enable (WEDE)—VCRB Bit 6
    492
    
    Flush Flag (FLSH)—VSTR Bit 1
    493
    
    Initialize Flag (INIT)—VSTR Bit 0
    493
    
    Internal Reserved Bits—Vcrb Bits 4, 7
    493
    
    Operation Complete (OPC)—VSTR Bit 4
    493
    
    Viterbi Status Register (VSTR)
    493
  - Figure 13-11 Viterbi Status Register (VSTR)
    493
    
    Data Output Buffer Full (DOBF)—VSTR Bit 9
    494
    
    Data Ready (DRDY)—VSTR Bit 6
    494
    
    Data Request (DREQ)—VSTR Bit 8
    494
    
    End Stage (ESTG)—VSTR Bit 7
    494
    
    Processing Done (DONE)—VSTR Bit 5
    494
    
    Reserved Bits—Vstr Bits 2, 3, 10–15
    494
- Figure 13-12 Viterbi Tap a Register (VTPA)
  495
- Viterbi Data Counter (VCNT)
  495
- Figure 13-13 Viterbi Tap Register B (VTPB)
  496
- Figure 13-14 Viterbi Trellis Setup Register (VTSR)
  497
  - Viterbi WED Setup Register (VWES)
    498
- Viterbi Bit Error Rate Register/Counter (VBER)
  497
- Figure 13-15 Viterbi WED Setup Register (VWES)
  498
- Table 13-6 Memory Addresses
  498
  - VWES Bits 7–0
    499
  - Window Length (WLEN[7:0])—VWES Bits 15–8
    499
- Viterbi Memory Access Register (VMEM)
  499
- Viterbi WED Data Register (VWED)
  499
- Chip Description
  500
- Table 13-7 Memory Modules Usage and Access
  500
- Figure 13-16 Viterbi Butterfly Structure
  503
- Viterbi Butterfly Implementation
  503
- Performance Analysis
  504
- Table 13-11 Performance of Various GSM Channels
  504
- Table 13-12 Variables for Calculating Processing Time
  504
- Programming Examples
  507
  - Channel Encode
    507
  - Channel Decode
    510
  - Including Read/Write Memory Access
    515
- References
  521
  - Section 14 Cyclic Code Co-Processor
    523
Section 14 Cyclic Code Co-Processor

524
- Introduction
  525
- Key Features
  525
- Figure 14-1 CCOP Block Diagram
  526
- CCOP Data FIFO Register (CDFR)
  530
- Figure 14-4 CCOP Count Register (CCNT)
  531
  - Continuous Mode (CM)—CCNT Bit 23
    532
  - Output Counter (OC[6:0])—CCNT Bits 22–16
    532
- Step Function Registers
  532
- Figure 14-5 Step Function Select Register (CSFS)
  533
- Figure 14-6 Step Function Table a Register (CSFTA)
  534
  - Input Enable Bits (INE[3:0])—CSFTB Bits 19–16
    535
- Figure 14-7 Step Function Table B Register (CSFTB)
  535
- Table 14-2 Step Function Table
  535
- Table 14-3 INE[3:0], OUTE[3:0] Bits and Their Respective Cfsrs
  536
- Figure 14-8 CCOP Control Status Register (CCSR)
  537
- Table 14-4 CCOP Operation Modes
  538
- Table 14-5 LRC Settings
  538
- Cyclic Code Processing Registers
  541
- Table 14-6 CCOP Interrupt Vectors
  541
  - Parity Coding Done Bit (PCDN)—CCSR Bit 23
    541
- Cipher Modes
  543
  - Normal Cipher Mode
    543
  - Operating Modes
    543
  - Step-By-Step Cipher Mode
    543
- Parity Coding Modes
  544
  - Parity Coding Mode Using One CFSR
    544
  - Using Two Concatenated Cfsrs
    544
  - Programming Considerations
    545
- Input Phase
  545
- Run Phase
  545
- Cipher Mode Processing
  546
- Output Phase
  546
- Table 14-7 Operations During Cipher Mode Processing
  547
  - Cipher Mode Initialization
    547
  - Cipher Mode Output
    547
  - Table 14-8 Operations During Parity Coding Processing
    548
  - Configuration Examples
    549
  - Parity Coding Mode Initialization
    549
  - Parity Coding Mode Output
    549
- Programming a General Circuit in Parity Coding Mode
  549
- GSM Fire Encode
  551
- GSM Fire Decode
  552
- Appendix A Bootstrap Code
  
  555
  - A.1 Bootstrap Code for the Dsp56305
    556
- Appendix B Equates
  
  569
  - B.1 Internal I/O Equates
    571
  - B.2 Interrupt Equates
    586
- Appendix C Jtag Bsdl
  
  589
  - C.1 Jtag Bsdl File
    591
- Appendix D Programming Reference
  
  601
  - D.1 Introduction
    603
  - D.1.1 Peripheral Addresses
    603
  - D.1.2 Interrupt Addresses
    603
  - D.1.3 Interrupt Priorities
    603
  - D.1.4 DMA Requests
    603
  - D.1.5 Programming Sheets
    603
  - D.1.6 HI32 Registers — Quick Reference Tables
    603
  - D.2 Internal I/O Memory Map
    604
  - D.3 Interrupt Addresses and Sources
    611
  - D.4 Interrupt Priorities
    613
  - D.5 Dma Request Sources
    615
  - D.6 Programming Reference Sheets
    616
  - Programming Reference
    624
    
    D.7 Quick Reference Tables
    642

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