Clock Signals - Motorola Digital DNA MSC8101 Technical Data Manual

1.3 Clock Signals

CLKIN
MODCK1
TC0
BNKSEL0
MODCK2
TC1
BNKSEL1
MODCK3
TC2
BNKSEL2
CLKOUT
DLLIN
Signal
Type
Name
Input Clock In
Primary clock input to the MSC8101 PLL.
Input Clock Mode Input 1
Defines the operating mode of internal clock circuits.
Output Transfer Code 0
Supplies information that can be useful for debugging bus transactions initiated by the
MSC8101.
Output Bank Select 0
Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.
Input Clock Mode Input 2
Defines the operating mode of internal clock circuits.
Output Transfer Code 1
Supplies information that can be useful for debugging bus transactions initiated by the
MSC8101.
Output Bank Select 1
Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.
Input Clock Mode Input 3
Defines the operating mode of internal clock circuits.
Output Transfer Code 2
Supplies information that can be useful for debugging bus transactions initiated by the
MSC8101.
Output Bank Select 2
Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.
Output Clock Out
The system bus clock.
Input DLLIN
Synchronizes with an external device.
Table 1-2. Clock Signals
Signal Description
Clock Signals
1-5