Host Master Receive Data Register (Hrxm); Host Transmit Data Register (Htxr) - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
If TWSD is cleared, the HI32 as the selected PCI target (HM = $1) in a read data phase
from the HRXS will insert PCI wait states if the HRXS is empty (HRRQ = 0). Wait states
will be inserted until the data is transferred from the DSP side to the HRXS. Up to eight
wait states may be inserted before a target initiated transaction termination
(disconnect-C/Retry) will be generated.
In a Universal Bus mode read from the HRXS the HI32 will insert wait states if the HRXS
is empty (HRRQ = 0). Wait states will be inserted until the data is transferred from the
DSP side to the HRXS.
Hardware, software and personal software resets empty the HRXS (HRRQ is cleared).
6.6.5

Host Master Receive Data Register (HRXM)

The HRXM is the output stage of the master DSP-to-host data path FIFO used for
DSP-to-host data transfers. The HRXM cannot be accessed by the DSP56300 core or the
host.
The HRXM transfers the data to the HI32 data signals via the data transfer format
converter (HDTFC). The value of the FC bits in the DPMC define which bytes of the
HRXM are output to the signals and their alignment. (See Section 6.5.9 and Table 6-5).
In the PCI mode (HM = $1) the DSP56300 core can clear the HI32 master-to-host bus data
path and empty HRXM by setting the CLRT bit in the DPCR.
In PCI DSP-to-host data transfers via the HRXM, all four byte lanes are driven with data,
in accordance with FC1-FC0 bits, regardless of the value of the byte enable signals
(HC3/HBE3-HC0/HBE0).
Hardware, software and personal software resets empty the HRXM.
6.6.6

Host Transmit Data Register (HTXR)

The HTXR is the input stage of the host-to-DSP data path FIFO used for host-to-DSP
data transfers. The HTXR cannot be accessed by the DSP56300 core.
The HTXR may be written if the HTRQ bit in the HSTR is set. Data should not be written
to the HTXR until HTRQ is set to prevent previous data from being overwritten. Filling
the HTXR by host processor writes, clears HTRQ.
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