Viterbi Wed Setup Register (Vwes); Figure 13-15 Viterbi Wed Setup Register (Vwes); Table 13-6 Memory Addresses - Motorola DSP56305 User Manual

VITERBI CO-PROCESSOR
Programming Model
while bits 5–0 define the address in it, see Table 13-7 below. The VBER is cleared when
Memory Access mode is enabled, and can be set to any valid start address. Every
read/write operation to any of the RAM modules increments the counter to the next
address location. When the VBER is cleared (and the VCOP is in Memory Access mode)
then loaded with another start address, every write to VMEM post-increments its value.
For accessing the Branch Metric RAM, the VBER value is taken as the Trellis state,
according to the state of the internal logic. For valid addresses of VCOP RAMs see Table
13-7.
Note: The Metric RAM is a 22-bit wide word RAM. The data accessed via VMEM
register occupies the 22 least significant bits, zero extended to bits [23:22].

13.5.11 Viterbi WED Setup Register (VWES)

The VWES is a 16-bit write-only setup register used to define the WED parameters.
The WED function is operational for block sizes of up to 256 decoded bits, that is,
≤
if VCNT 256.
15 14 13 12
WLEN7 WLEN6 WLEN5 WLEN4 WLEN3 WLEN2 WLEN1 WLEN0 WSTR7 WSTR6 WSTR5 WSTR4 WSTR3 WSTR2 WSTR1 WSTR0

Figure 13-15 Viterbi WED Setup Register (VWES)

13-28

Table 13-6 Memory Addresses

Memory Size
VP 32 x 16
Reserved 7 x 16
WED 64 x 16
Path Metric 64 x 22
DELAY 45 x 16
11 10 9
DSP56305 User's Manual
VBER[7:6] VBER[5:0]
00
01
00
10
11
8 7 6 5
$0 – $1F
$0 – $6
$0 – $3F
$0 – $3F
$0 – $2C
4 3 2 1
MOTOROLA
0
AA1324