Essi Control Register A (Cra) - Motorola DSP56305 User Manual

7.4.1

ESSI Control Register A (CRA)

The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers used
to direct the operation of the ESSI. The CRA controls the ESSI clock generator bit and
frame sync rates, word length, and number of words per frame for the serial data. The
CRA control bits are described in the following paragraphs (see Figure 7-6).
7.4.1.1 Prescale Modulus Select (PM[7:0]) CRA Bits 7-0
The PM[7:0] bits specify the divide ratio of the prescale divider in the ESSI clock
generator. A divide ratio from 1 to 256 (PM = $0 to $FF) may be selected. The bit clock
output is available at the transmit clock signal (SCK) and/or the receive clock (SC0)
signal of the DSP. The bit clock output is also available internally for use as the bit clock
to shift the Transmit and Receive Shift Registers. The ESSI clock generator functional
diagram is shown in Figure 7-13. F
frequency as the CLKOUT signal, when that signal is enabled). Careful choice of the
crystal oscillator frequency and the prescaler modulus will allow the industry-standard
codec master clock frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz to be
generated. Both the hardware reset signal and the software reset instruction clear
PM[7:0].
7.4.1.2 Reserved CRA Bits 8-10
These bits are reserved. They are read as 0 and should be written with 0.
7.4.1.3 Prescaler Range (PSR) CRA Bit 11
The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler.
This bit is used to extend the range of the prescaler for those cases where a slower bit
clock is desired. When PSR is set, the fixed prescaler is bypassed. When PSR is cleared,
the fixed divide-by-eight prescaler is operational (see Figure 7-13).
Note: This definition is reversed from that of the 560xx SSI.
The maximum allowed internally generated bit clock frequency is the DSP56305 internal
clock frequency divided by 4 (F
clock frequency is the DSP56305 internal clock frequency divided by 4096 (F
Both the hardware reset signal and the software reset instruction clear PSR.
The combination PSR = 1 and PM[7:0] = $00 (dividing F
Note:
synchronization problems and should not be used.
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
is the DSP56305 core clock frequency (the same
core
/4); the minimum possible internally generated bit
core
DSP56305 User's Manual
ESSI Programming Model
/4096).
core
by 2) may cause
core
7-15