Table 9-1 Prescaler Source Selection; Prescaler Preload Value Pl[20:0] — Tplr Bits 20-0; Prescaler Source Ps[1:0] — Tplr Bits 22-21; Reserved Bit — Tplr Bit 23 - Motorola DSP56305 User Manual

Timer/Event Counter
Timer/Event Counter Architecture
9.2.4.1 Prescaler Preload Value PL[20:0] — TPLR Bits 20-0
These 21 bits contain the prescaler preload value. This value is loaded into the prescaler
counter when the counter value reaches zero or the counter switches state from disabled
to enabled.
If PL[20:0] = N, then the prescaler counts N+1 source clock cycles before generating a
prescaler clock pulse. Therefore, the prescaler divide factor = (preload value) + 1.
The PL[20:0] bits are cleared by a hardware RESET signal or a software RESET
instruction.
9.2.4.2 Prescaler Source PS[1:0] — TPLR Bits 22-21
The two Prescaler Source (PS) bits control the source of the prescaler clock. Table 9-1
summarizes PS bit functionality. The prescaler's use of a TIO signal is not affected by the
TCSR settings of the timer corresponding to the TIO signal being used.
If the prescaler source clock is external, the prescaler counter is incremented by signal
transitions on the TIO signal. The external clock is internally synchronized to the internal
clock. The external clock frequency must be less than the DSP56305 internal operating
frequency divided by 4 (CLK/4).
The PS[1:0] bits are cleared by a hardware RESET signal or a software RESET instruction.
To ensure proper operation, change the PS[1:0] bits only when the prescaler
Note:
counter is disabled. Disable the prescalar counter by clearing the TE (TCSR Bit
0) bit in each of the three timers.
PS1
9.2.4.3 Reserved Bit — TPLR Bit 23
This reserved bit is read as 0 and should be written with 0 for future compatibility.
9-6

Table 9-1 Prescaler Source Selection

PS0 PRESCALER CLOCK SOURCE
0 0
0 1
1 0
1 1
DSP56305 User's Manual
Internal CLK/2
TIO0
TIO1
TIO2
MOTOROLA